Cadence secured TSMC A14 design tool certification, reducing AI chip design iteration cycles by 2.5x in the race toward agentic AI accelerators.

Cadence and TSMC have expanded their collaboration with Cadence achieving tool certification for TSMC's advanced A14 process technology, demonstrating an industry-leading UALink solution in TSMC N3P, and introducing new silicon-proven IP for N3P and N2P technologies. The companies are now enabling agentic AI chip and 3D-IC design flows across TSMC's N3, N2, A16, and A14 process technologies, including TSMC 3DFabric support for wafer-scale systems with hundreds of chiplets.

"Cadence's partnership with TSMC continues to deliver breakthrough innovations that enable leading-edge customers to accelerate their most advanced semiconductor designs," said Chin-Chi Teng, senior vice president and general manager of the Digital and Signoff Group at Cadence. "With AI-driven design flows, silicon-proven IP and 3D-IC solutions, we're helping customers achieve faster time to market and improved PPA on TSMC's leading-edge process technologies."

Cadence's digital full flow, signoff flow, and custom/analog flows are now certified for TSMC A16 and A14 process technologies. The digital full flow features the Innovus Implementation System, Cadence Cerebrus Intelligent Chip Explorer for DTCO, and enhanced signoff tools including the Tempus Timing and ECO Solution, EMX Planar 3D Solver, Voltus IC Power Integrity Solution, Quantus Extraction Solution, Pegasus Verification System, the Liberate Characterization Portfolio, and the Genus Synthesis Solution. For custom and analog design, Virtuoso Studio solutions include design-rule-correct layout generation and automated design migration to TSMC A16 and A14, reducing iterations by up to 2.5X and improving first-pass success for AI, HPC, and mobile SoCs.

On the A14 IP front, UCIe-64G has been taped out, LPDDR6 IP is in development, and Artisan Foundation IP and mixed-signal IP are expected to be available in Q4 2026, including standard cells, GPIO, and Memory Compilers for HPC/AI and networking applications. Cadence analog, digital, and signoff tool flows have also been certified for TSMC N2P, with the Virtuoso Layout Suite adding enhanced connectivity models for a production-ready custom design environment. Taped-out N2P IP includes DDR5, LPDDR5, and PCIe 6.0, with PCIe 3.0 IP expected to tape out in Q4 2026. UCIe-64G IP on N2P silicon is in the testing lab and has been characterized on N3P.

Cadence solutions now support TSMC SoW-X full design flow with hundreds of chiplets and millions of bumps, 5X reticle-size CoWoS-L-style advanced packages, and integration of SoIC, eDTC, MIMCap, IVR, HBM logic base die, and substrate using Integrity 3D-IC for system planning and assembly. A pre-simulation-driven, die-to-die auto-routing flow is certified with the Cadence Allegro Substrate Router and OmniRoute Advanced Interconnect Router, automatically deriving signal-integrity-optimized routing strategies across all CoWoS architectures and targeting UCIe requirements. TSMC-COUPE Compact Universal Photonic Engine high-bandwidth photonic-to-silicon connectivity is enabled for integration with Cadence 224G SerDes IP, aligned with the UALink, ESUN, UltraEthernet, and CPO ecosystems.

Global Unichip Corp. leverages Cadence solutions to deliver advanced custom silicon for AI accelerators and hyperscale systems on TSMC's leading-edge process technologies. "As designs scale to leading-edge TSMC process technologies such as N3P and N2P, success depends on tightly optimized execution across increasingly complex system requirements—especially when working with the early-adopters where schedule risk is highest," said Louis Lin, senior vice president at Global Unichip Corp. "Cadence's solutions provide the predictability, performance, and silicon correlation we need to successfully deliver and tape out complex designs on TSMC's most advanced nodes."

Cadence and TSMC are transforming next-node AI and HPC design from a scramble into a more complete stack. Certified A14, A16, and N2P flows, silicon-proven interconnect and memory IP, and 3DFabric support for hundreds of chiplets give customers a clearer path from first silicon to wafer-scale systems, with less process risk and faster time to market.