Why OpenAI Is Dual-Sourcing Next-Gen AI Chips at TSMC and Samsung, September 2026

OpenAI's confirmation that its next-generation AI processors will be split between TSMC and Samsung signals that AI chip volumes have grown beyond what any single foundry can absorb, as TSMC's 2nm wafers are reportedly priced at $30,000 each and CoWoS packaging capacity is constrained into mid-2027.

OpenAI's confirmation this week that its next-generation AI processors could be manufactured at Samsung alongside TSMC — a deliberate dual-sourcing arrangement — marks more than a procurement adjustment. For a company that has consistently defined the outer edge of AI compute demand, the decision to spread foundry risk at this scale implies that the volume requirements for its internal silicon have crossed a threshold that no single manufacturer, including TSMC, can absorb on its own. The disclosure crystallizes a tension that has been building across the AI supply chain throughout 2026: the gap between semiconductor demand and foundry capacity is not a transient shock but a structural condition, one that is forcing the world's largest AI developers to plan their silicon sourcing years in advance.

TSMC's centrality to this pressure is written clearly in the numbers. The company reported revenue growth of 45 percent year-on-year as of August 2026, driven by orders from Nvidia, AMD, and Apple. Its capital expenditure for FY2024 reached 956.01 billion TWD — a 33 percent intensity against 2.89 trillion TWD in revenue, placing TSMC first among chip peers by absolute investment. Reports citing analyst estimates suggest the company's 2026 capital expenditure could approach $64 billion, as fab equipment orders have nearly doubled within six months amid persistent tool shortages. TSMC's 2nm wafers are reportedly priced at approximately $30,000 each, with capacity said to be booked through 2028. The Longtan site, revived this summer for 1.4nm fabrication and CoWoS packaging, was fully sold out at launch. Jensen Huang reportedly made a low-key visit to Taiwan in August ahead of Nvidia's quarterly earnings to lock down wafer and packaging capacity with TSMC executives, while AMD separately committed more than $10 billion to advanced packaging expansion with TSMC in Taiwan — both episodes illustrating that hyperscalers and AI chipmakers now treat foundry access as a strategic imperative rather than a downstream procurement line item.

The constraint most likely to define 2026 and 2027, however, is not at the front end of fabrication but in advanced packaging. TSMC's CoWoS technology — which integrates logic and memory in high-density chiplet stacks — became the visible bottleneck for Nvidia's accelerator supply chain earlier this year. Supply chain reporting indicates that CoWoS capacity limitations will extend into mid-2027, with all available HBM capacity for 2026 already fully committed. TSMC has responded by expanding outsourcing of key packaging steps to Samsung, Intel's packaging subsidiary, and facilities in Japan, and by opening a dedicated supplier campus in Kaohsiung to compress validation timelines for CoWoS and related processes. Yet Foxconn's chief executive stated after record second-quarter 2026 earnings that CoWoS remains the effective ceiling for AI server assembly through 2027. More recently, TSMC has flagged that ABF substrates — not CoWoS capacity itself — are emerging as the next binding constraint, as the CoWoS availability gap gradually narrows while substrate supply has not kept pace. An unexpected delay in HBM production further complicates the picture: TSMC's hybrid bonding process is advancing at a six-micron node resolution, and any slippage in the HBM stack could constrain packaging throughput for next-generation accelerators regardless of available wafer supply.

Looking further out, TSMC's roadmap is oriented toward sustaining process leadership as the competitive surface shifts. The company has disclosed plans to begin deploying High-NA EUV lithography in 2030, with its A10 or A11 process generations identified as the likely candidates. ASML has simultaneously locked in adoption commitments from TSMC, Samsung, and Intel for its High-NA machines, which are reported to deliver a 40 percent throughput improvement through larger reticle designs — underscoring how equipment supply constrains the pace of node transitions across the entire industry rather than at any single foundry. Geopolitical factors introduce longer-horizon uncertainty: Huawei is reportedly accelerating development of domestic lithography equipment, and scrutiny of TSMC-manufactured chips — including those produced at TSMC's Arizona facility — appearing in Chinese AI systems has intensified in national-security discussions on both sides of the Pacific. Intel's $20 billion capital raise this summer signals investor conviction that the foundry competitive race remains open, even as neither Intel nor Samsung has demonstrated the yield or throughput at the leading edge to displace TSMC in the near term.

The picture at this juncture is of a company simultaneously at peak demand and peak operational complexity. Pricing power and revenue momentum are clearly favorable: constrained capacity, leading-node wafer pricing, and a client roster spanning every significant AI hardware program give TSMC a commercial position its nearest competitors cannot currently match. The risks, however, are structural and compounding: geopolitical exposure concentrated in Taiwan, deep customer concentration, the capital intensity required to stay at the frontier — TSMC's highest reported capex reached 1.08 trillion TWD in the period ending December 2022 — and the possibility that packaging bottlenecks at CoWoS or ABF substrates constrain revenue regardless of how strong wafer demand remains. Three signals warrant close attention in the quarters ahead: whether the silicon TSMC produces for OpenAI compares favorably against the Samsung-sourced alternative, which would recalibrate assessments of TSMC's process moat; the pace at which ABF substrate supply expands, which supply chain analysis identifies as the binding variable for 2027 AI server assembly; and TSMC's quarterly capex guidance through FY2026, which will indicate whether record equipment orders are translating into effective new capacity or simply elongating the forward booking backlog.