Friday, September 11, 2026
AI 인프라 · 뉴스 & 분석
반도체·하드웨어리포트
반도체·하드웨어 · 리포트

TSMC는 2030년부터 High-NA EUV 리소그래피를 도입할 계획을 공개했으며, A10 또는 A11 공정 기술이 주요 후보로 선정됐다.

차세대 로직 제조를 위한 명확한 로드맵을 제시하여 상류 장비 발주를 촉진하고 장기적인 GPU/어셀러레이터 아키텍처 로드맵을 형성한다.
업계 전문지Slicast · September 9, 2026 · 글로벌 · 출처: Tom's Hardware
중요도 80

For years, TSMC avoided public comment regarding its plans to adopt extreme ultraviolet (EUV) lithography with 0.55 numerical aperture optics, known as High-NA EUV. Internal development teams had successfully advanced process technologies without relying on $400 million High-NA scanners. Nevertheless, TSMC can no longer depend indefinitely on Low-NA EUV systems. This week, the company officially announced it will begin using High-NA EUV lithography in 2030.

TSMC did not formally specify which fabrication node will first adopt High-NA EUV, though the 2030 timeline highlights several candidates. The company noted that the number of layers processed with High-NA EUV will gradually increase as fabrication technologies grow more complex. This trend is driven by increasingly intricate transistor architectures, likely pointing toward more advanced implementations of gate-all-around (GAA) transistors and complementary field-effect transistors (CFETs) in the future.

TSMC plans to initiate high-volume manufacturing with High-NA EUV tools in 2030, utilizing conventional 6×6-inch photomasks. In 2031, the company will establish a pilot line operating with 6×12-inch photomasks, aiming to integrate full 6×12-inch High-NA lithography systems into advanced node production by 2033.

High-NA EUV tools deliver an 8nm single-exposure resolution, compared to the 13nm resolution provided by current Low-NA EUV systems. When paired with standard 6×6-inch photomasks, however, High-NA scanners offer only half the exposure field of their Low-NA predecessors, complicating the manufacture of large dies. Consequently, chipmakers developing massive AI accelerators must either stitch multiple exposure fields together or adopt multi-chiplet architectures—both of which introduce additional hurdles regarding tool productivity and power consumption. To overcome these 6×6-inch mask constraints, TSMC is collaborating with ASML to prepare the industry for 6×12-inch photomasks.

Scaling photomask dimensions is a complex undertaking requiring updates across the entire ecosystem, from electronic design automation (EDA) software to mask fabrication, writing, and handling equipment. This shift demands coordinated industry-wide effort. ASML remains optimistic about the transition, noting strong backing from Intel, TSMC, and Samsung.

“We expect the adoption of High NA EUV to increase progressively along the device scaling roadmap, first using current 6-inch masks and then further supported by 12-inch masks, which enable greater scanner productivity and allow the industry to meet the demand for smaller, faster and more energy-efficient chips,” said Christophe Fouquet, president & CEO, ASML. “We are pleased by the strong initial support of semiconductor manufacturers, mask suppliers and partners for this initiative.”

The most closely watched question surrounding TSMC’s High-NA EUV deployment is which process node will first utilize the technology. Based on TSMC’s published roadmap, A10 or A11 (the 1nm/1.1nm-class nodes) appear to be the strongest candidates for deploying High-NA EUV scanners on the most critical layers. TSMC currently structures its roadmap into annual client-focused nodes (N2, N2P, N2X, A14, A13) and roughly biennial high-performance nodes (A16 in 2027, followed by A12 in 2029). The company has confirmed that both A12 and A13, scheduled for 2029, will continue to rely on conventional EUV lithography.

Because A13 represents an optical shrink of A14, delivering only a 6% increase in transistor density while leaving performance and power gains undisclosed, its 2030 successor will need to provide substantially more significant advancements. It is therefore logical to anticipate that A13’s follow-on node—whether designated A11 or A10—will incorporate advanced lithography techniques and/or TSMC’s third-generation nanosheet GAA transistors. These innovations would aim to achieve markedly higher transistor density alongside meaningful performance and power improvements. As always, this remains speculative pending official confirmation.

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