TSMC warned that ABF substrate shortages—not CoWoS—will become the next critical bottleneck for advanced AI chip packaging as CoWoS capacity gaps narrow.
At the OCP APAC Summit on August 11, TSMC Vice President of Advanced Packaging Technology and Services He Jun announced that CoWoS (Chip-on-Wafer-on-Substrate) capacity has doubled for three consecutive years, with supply now "very close" to market demand. However, the advanced packaging supply chain bottleneck is shifting from memory to ABF substrates, which He Jun warned could become the second most critical constraint on AI chip expansion in the coming years, trailing only memory.
He Jun, widely known as "Mr. CoWoS," emphasized that relentless demand for AI computing power is driving rapid evolution in advanced packaging architectures. The 5.5x reticle size CoWoS is now in high-volume production, with yields consistently exceeding 98% across multiple AI customer products, with some reaching 99%. TSMC is maintaining an annual rhythm of introducing new CoWoS technology and expects to advance packaging size to 14x reticle by 2029.
The critical bottleneck, however, lies upstream in materials. ABF substrate supply remains concentrated among a handful of Japanese and Taiwanese manufacturers. The increasing size and packaging complexity of AI accelerators are driving sharply higher demand for ABF substrates, and customers have already begun sourcing from multiple suppliers to diversify risk. Yet this creates new challenges: variations in thermal and mechanical characteristics among different manufacturers threaten manufacturing consistency.
Development cycles have been compressed dramatically through collaborative supplier validation—from an average of one generation every two years to one generation per year—but the ABF substrate supply-demand gap continues widening. Global substrate manufacturers have collectively planned investments of $19.1 billion to expand capacity, yet this remains insufficient. Upstream raw material suppliers, such as glass fabric producers, are expected to gradually release new capacity starting in 2027, but expansion continues to lag behind AI chip demand growth.
For large-format packaging exceeding 3x reticle, all component quality standards must meet automotive-grade specifications or higher to maintain acceptable failure rates. This raises the bar for material and manufacturing precision across the entire supply chain.
TSMC projects that SoIC (System on Integrated Chips) technology—now entering a high-growth phase—will expand at a compound annual growth rate exceeding 90% from 2022 to 2027. The 6-micron hybrid bonding pitch has entered mass production, with plans to shrink further to 4.5 microns by 2029 for direct A14 logic chip-on-A14 logic chip stacking. This enables true vertical integration using the most advanced process technology and delivers over 50 times the interconnect density of traditional solutions while improving power efficiency by approximately five times. This advantage is particularly critical for AI systems, where data movement between chips increasingly becomes the power bottleneck. By reducing chip-to-chip distances and increasing interconnect density, the power consumption required for data transmission can be significantly reduced.
He Jun described his daily work managing advanced wafer manufacturing as running "the world's largest online matchmaking service," where customers provide complex algorithms and TSMC finds the most suitable "soulmate" for each die. TSMC leverages chiplet "smart matching" technology to recombine performance-complementary bare dies, reducing waste from individual chip performance variations and improving overall yield.
The interposer's function is also evolving from simple interconnection toward deeper integration, potentially carrying active bridge chips, integrated voltage regulators, capacitors, and silicon photonics devices to form a comprehensive system-level packaging platform.
Facing increasingly complex heterogeneous integration challenges, He Jun stressed the growing importance of "System Technology Co-Optimization" (STCO). As CoWoS packaging sizes enlarge, component-level development and validation alone prove insufficient; chip, packaging, and system conditions must be considered together. TSMC is promoting parallel development among customers, suppliers, and fabs, releasing system specification guidelines six quarters before mass production and stationing supplier R&D teams near fabs to accelerate collaborative problem-solving on thermal, mechanical, and power issues.
The future development of AI advanced packaging will ultimately depend not on any single company, He Jun concluded, but on collaborative evolution across the entire ecosystem of chips, packaging, materials, equipment, and system integration. As CoWoS scales and SoIC hybrid bonding pitches shrink, synchronizing the evolution of each link through STCO, rapid validation, and continuous feedback will prove essential to sustaining progress in AI advanced packaging.