TSMC 2nm advanced process wafers priced at $30,000 per unit with production capacity fully booked through 2028

TSMC has started shipping chips on its newest 2-nanometer process, and the price tag attached to that milestone is reshaping what every major chipmaker will pay for silicon over the next two years. A single 300mm wafer processed on the company's N2 node now costs roughly $30,000, according to pricing data reported by Tom's Hardware and corroborated by the semiconductor research firm TrendForce. That represents a sharp increase from the $18,000 to $20,000 TSMC charged for its outgoing N3 (3-nanometer) node just a few years earlier. The company's order books for N2 are already full into 2028.

TSMC began ramping N2 production in the second half of 2025, running two fabs in Hsinchu and Kaohsiung simultaneously—a pace the company had not attempted at a comparable stage of any earlier node. Internal targets called for around 30,000 wafers a month by the end of 2025, based on reporting from Tom's Hardware. Semiconductor tracking firm Silicon Analysts pegs a further step-up to roughly 60,000 wafers a month at Hsinchu's Fab 20 by the fourth quarter of 2026, with additional capacity due at TSMC's US sites afterward.

Demand has outrun even that accelerated build-out. Lead times for N2 and the related A16 node now stretch 78 to 156 weeks, and both are booked well into 2028, per Silicon Analysts' foundry allocation tracking. That is an unusually long queue for a node that only reached volume production a matter of months ago, reflecting as much customer appetite for AI and high-performance computing silicon as it does TSMC's manufacturing pace.

TSMC does not publish official wafer prices, so every figure in circulation traces back to supply-chain reporting rather than a company price list. The most consistent number across outlets puts N2 wafers at approximately $30,000, roughly 20% to 50% above N3 depending on the report and customer volume tier. TrendForce's own analysis estimated the real increase at closer to 10% to 20% once extreme claims were checked against customer contracts.

Layered on top of the per-wafer cost is a separate, steeper number. Developing a single 2nm chip platform now runs to roughly $725 million, covering the full family of chips built on that platform rather than one part. That cost ceiling explains why only a handful of companies—Apple, AMD, Nvidia, and Qualcomm among them—can justify being early N2 customers at all.

Part of the price jump is technical rather than purely a supply-and-demand story. TSMC's follow-on A16 node, expected in the second half of 2026 at a rumored $45,000 per wafer, adds backside power delivery, a manufacturing step that moves power routing to the underside of the chip and frees the front side for signal wiring. The process requires bonding the wafer face-down to a carrier, grinding it down from the back, and adding a fresh layer of interconnects. Those extra steps show up directly in the quote a customer receives.

The relationship between wafer cost and finished chip cost is not one-to-one. It compounds through yield and die size: a higher wafer price combined with a lower early-life yield rate both push costs upward simultaneously, which is why a node-over-node wafer premium of 20–50% can translate into an even larger jump in the cost of a finished, packaged chip.

Reported TSMC wafer prices have climbed steadily for two decades, but the pace has accelerated at the leading edge. Despite the price, TSMC has not struggled to fill its order book. AMD has confirmed first silicon for its next-generation EPYC server processor, codenamed Venice, built on N2, and Fujitsu has done the same for its own chips. MediaTek is said to be finishing design work for its next-generation Dimensity mobile chip on N2, and Qualcomm is reportedly developing the third generation of its Snapdragon 8 Elite platform on the same node. Apple, historically TSMC's largest and earliest customer on any new node, is widely expected to bring its next A-series and M-series chips to N2, though the company has not confirmed this.

Apple's historical advantage in pricing reflects its volume. The company has paid less per wafer than its industry peers because of the sheer size of its orders, per Tom's Hardware's reporting on foundry pricing dynamics. That leaves AMD, Qualcomm, Nvidia, and Intel negotiating individually, with prices tied to both total volume and the share of that volume built on the leading-edge node.

TSMC's own financial results underscore the demand story. The company reported second-quarter 2026 revenue of $40.2 billion, up 36% year over year and at the high end of its guidance range. Gross margin came in at 67.7% and operating margin at 60.3%, both above the company's own forecast range. TSMC raised its full-year 2026 capital expenditure guidance to between $60 billion and $64 billion.

Advanced nodes of 7nm and smaller made up 77% of wafer revenue in the quarter, split between 5nm (33%), 3nm (30%), 7nm (11%), and 2nm, which is still ramping, at about 3%. High-performance computing, the category that includes AI accelerators, climbed to 66% of total revenue, up from 58% a year earlier, while smartphone revenue slipped to 17% of the mix. TSMC also confirmed an additional $100 billion investment at its Arizona campus, on top of previously announced spending there.