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ChangXin Memory (CXMT) DRAM wafers cost 54% more per square millimeter than TSMC's N2 advanced logic process despite requiring simpler fabrication.

CXMT's persistent cost disadvantage versus advanced logic fabs constrains competitive viability in cost-sensitive memory markets without sustained government subsidies.
업계 전문지Slicast · 2026년 9월 24일 17:34 UTC · 미국 · 출처: Wccftech
중요도 70

In what is a testament to the craziness of the contemporary AI buildout age, 1b DRAM is now costlier per square millimeter than TSMC's N2 wafer, despite being considerably easier to fabricate.

A square millimeter of 1b DRAM costs $0.654, while TSMC's N2 wafer costs $0.424 per square millimeter.

According to Kernel Insight and as quoted by ZDNet, the price of a 300-millimeter TSMC N3 (3nm) wafer is around $20,000, while the N2 wafer of the same size goes for around $30,000. This equates to a per-square-millimeter price of $0.283 for N3 and $0.424 for N2.

The 1b DRAM has a bit density of 0.436 Gb per square millimeter. At a reference price of $1.50 per Gb, this equates to a cost of around $0.654 per square millimeter, which is approximately 54 percent more expensive than TSMC's N2 wafer.

On September 21, DRAM Exchange disclosed a price of $24.80 for a 16 Gb DDR5 eTT, which equates to around $1.55 per Gb. For all intents and purposes, the $1.50 per Gb reference price is an appropriate estimate.

Even the multi-generation-old 1z DRAM is nearly equivalent to TSMC's cutting-edge node on a per-square-millimeter basis, given its bit density of 0.273 Gb per square millimeter, which equates to a reference cost of around $0.410 per square millimeter.

Critically, the fabrication of DDR5 is considerably easier than an equal-sized silicon wafer on TSMC's N2 node. Yet in testimony to the ongoing chronic shortage of commodity DRAM, 1b DDR5 is currently priced at a ~50 percent premium to TSMC's cutting-edge wafer.

This pricing paradigm is not expected to normalize anytime soon, especially as Samsung's B1b process—its first sub-10nm DRAM fabrication process, officially renamed D0a—fabricates memory cells and surrounding driver circuitry (the peri) on separate wafers and then joins them via wafer-to-wafer hybrid bonding, stacking the memory cells atop the peri. Because hybrid bonding is quite expensive, Samsung will likely price the next-generation DRAM at an eye-watering premium.

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ChangXin Memory (CXMT) DRAM wafers cost 54%… · Slicast