AMD's Epyc X-chips return after a three-year hiatus with Venice-X, which promises big speedups for EDA and HPC workloads.
AMD's cache-packed Epyc X chips are officially making a comeback. Based on the frequency-optimized SKUs we looked at in September, the HPC-optimized Venice-X parts will offer up to 96 cores and use the company's 3D V-Cache chip stacking technology to triple L3 cache density to more than a gigabyte.
Don't expect them soon, though. AMD expects Venice-X to begin trickling out in the second half of 2027. First teased at CES earlier this year, the chips are aimed primarily at latency-sensitive technical and scientific computing workloads such as computational fluid dynamics and electronic design automation (EDA).
AMD itself relies heavily on its X-series Epycs for EDA workloads like functional verification testing, which simulates silicon to ensure it behaves as intended. According to AMD Fellow Phil Steinke, keeping more of the model in cache means the CPU cores don't have to wait as long for data to move in and out of system memory.
Normally, boosting L3 capacity would require larger chiplets, which have lower yields. For the past four years, however, AMD has taken a different approach, using advanced packaging to give its existing CPU dies a small SRAM backpack.
The technology has been around for several generations, debuting in the Ryzen 7 5800X3D in 2022. That consumer desktop chip stacked a 64 MB SRAM tile on an 8-core chiplet, raising L3 capacity to 96 MB. The extra cache made it one of the most potent gaming CPUs of its time. Later that year, AMD brought the same technology to its Milan generation of Epycs as it expanded its portfolio to address a wider range of workloads. The extra cache was popular enough to justify a second generation of X-series Epycs, which launched in 2023.
After that, nothing. When AMD unveiled its 5th-gen Epycs in late 2024, there was no Turin-X on the roadmap. According to Madhu Rangarajan, who runs AMD's compute and enterprise AI products business, this was intentional. "We are not doing the X every generation.... The enterprise HPC kind of market tends to have a cadence that's a little bit slower, so that's what drives our cadence."
Venice-X marks the return of AMD's X-chips, and for the most part it follows the same recipe as its predecessors. Each of the chip's up to eight CPU dies is now bonded to a 96 MB SRAM tile using advanced packaging, for a total of 144 MB of L3 per chiplet, or 1,152 MB per socket. That is the same as the Genoa-X parts they replace.
Core count and cache capacity haven't increased, but clock speeds have. Venice now hits 5.3 GHz, compared with just 3.7 GHz for Genoa-X. "In Milan and Genoa, there was one trade-off. You either had to choose something that was high frequency or you chose something with 3D V-Cache." HPC customers want both, Rangarajan told El Reg.
The stacking method required that compromise. Placing SRAM on top of the compute chiplets boosted L3 caches but also trapped heat, which limited boost clocks. For the Zen 5 generation, AMD moved the SRAM tile from the top of the stack to the bottom. With the SRAM no longer acting as a heat-trapping blanket, the chips could run hotter and faster for longer. Gamers have enjoyed these higher clocks and bigger caches on AMD's Ryzen 9000 processors, and with Venice-X, those improvements are finally making their way into Epyc.
Because customers no longer have to choose between big caches and fast clocks, Rangarajan believes the chip may see wider adoption. "I think it's going to end up being much bigger in HPC than the previous generations where we had to make that tradeoff."
Curiously, if frequency weren't a priority, Venice-X might not need 3D stacked SRAM at all. As we reported earlier this year, AMD's top-specced Venice CPUs boast 256 cores and 1,024 MB of L3 cache. AMD could have simply fused off 160 of the cores to achieve a similar cache-per-core ratio. It did something similar for Turin: the Epyc 9175F is essentially a 128-core part with 112 cores fused off, leaving a 16-core chip with 512 MB of last-level cache.
"You could do that [with Venice], but then you don't get the frequency part of it. The Fmax would be at 4.1 gigahertz and not 5.3 GHz," Rangarajan said.
"Venice X really changes the game," he added. "For the first time, you can get the larger L3 in our highest frequency part."