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AMD's VP and chief Zen architect pushed back on claims by Nvidia and Arm that their CPUs were built for agentic AI, saying the company did not foresee agentic workloads four years ago, as AMD launched its Zen 6 EPYC Venice CPUs.

The dispute is a marketing battle over which CPU architecture suits agentic AI workloads, and it could influence how enterprises and cloud buyers specify host CPUs for inference-heavy orchestration.
Trade pressSlicast · November 10, 2026 at 17:20 UTC · Global · Source: Tom's Hardware
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Two prominent voices at AMD agree that the company did not design its new Zen 6 family, codenamed Venice, explicitly for agentic AI. The comments read as a clear shot at Nvidia and Arm, which have both described their latest data center CPUs as "agentic" in nature. In separate talks, AMD's chief Zen architect Mike Clark and corporate VP Madhu Rangarajan said the company did not predict the agentic wave when Zen 6 development began.

CPU development cycles are measured in years. The agentic frenzy around CPUs only took hold around March of this year, so it is unreasonable to expect anyone to have developed silicon specifically for agentic AI, let alone a general-purpose data center CPU. Still, Nvidia claims its Vera CPU was "purpose-built" for agentic AI, and Arm says its AGI CPU was "designed for the demands of agentic AI."

"We think that the EPYC 9006 CPU is the best CPU for the agentic era, and spoiler alert, we didn't magically know four years ago that agentic was going to be a thing and purpose-built something for agentic," said Rangarajan in a session with media. "The reality is an agentic workflow is a diverse set of tasks… and in order to execute those tasks well, you need compute that is able to handle a diverse set of workloads with a full portfolio."

Mike Clark agreed with the sentiment when introducing the Zen 6 microarchitecture: "I'm not going to mislead and act like I knew agentic computing was coming, or we knew it, but we did strongly believe that the CPU would always have a place in the software ecosystem of AI… And as agentic [has] blown up, we [are] able to now deploy that for agentic compute workloads."

As AMD rolls out its next-generation microarchitecture with Venice, it is targeting the messaging from Arm and Nvidia, which have posed the most direct threat to AMD's continued rise in the data center on the back of agentic workloads. There are performance vectors where Nvidia's Vera looks strong for agentic workloads, as shown in our Nvidia Vera testing. AMD's argument is that agentic AI calls for a broad range of CPUs, just as general-purpose workloads do, and it is pushing back on the single-SKU approach of Nvidia and Arm.

Our testing of two AMD Venice chips supports that argument. The dense EPYC 9996, with 256 cores and 512 threads, offers peak throughput, while the frequency-optimized EPYC 9686F goes toe-to-toe with Vera in the role of an AI host node. AMD is launching two more ranges next year: Venice-X, which targets HPC with 3D-stacked cache, and Verano, which goes directly after Vera as an AI host node with an LPDDR5X memory system.

The workload characteristics of agentic AI are still being defined, but we understand how those loops work better now than we did at the beginning of the year. As with most complex topics, the answer to what matters in a CPU for agentic AI is the always-disappointing "it depends."

As we break down in our early testing procedure for agentic AI, the workload characteristics and demand on the CPU and memory are defined by what the agent is doing and, in the data center, by what several agents are doing at high concurrency when sandboxed. A coding agent will generally call more tools that tax the CPU than a web browsing agent does, for example, while an agent that queries a database may call for strong memory performance. Some performance characteristics cannot be addressed with different SKUs, such as that strong memory performance. Even so, the potential diversity of agentic workloads makes a strong case for CPU variety.

At the most basic level, an agentic loop allows the LLM to understand the functions you have defined and then pass arguments to those functions to execute them. The workload can be as broad as anything you can define in a function in languages like Python and Rust.

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AMD's VP and chief Zen architect pushed back… · Slicast