AMD's EPYC 9006 'Venice' platform and Zen 6 architecture have launched, with ServeTheHome publishing its benchmark results.
At long last, the day is here. Today we finally get to share our first look at AMD's EPYC "Venice" series, the EPYC 9006 processors. Following AMD's biennial CPU development roadmap, the highlight of the year for AMD's CPU teams is the launch of the EPYC 9006 processors and the Zen 6 CPU architecture that underlies them. Amid an unprecedented explosion in demand for server CPUs for AI systems driving both host nodes and agentic workloads, AMD is in a commanding position, bringing to market a new generation of even more powerful server hardware right when the industry needs it most. AMD also has ambitions of becoming the undisputed market leader for server CPUs, and Venice seems primed to help it get there.
As far as server CPU launches go, today's launch is remarkable on multiple levels. Taking a look at a wholly new server platform from AMD, socket and all, would normally be a big event in and of itself. However, the server boom has turned the CPU development cycle on its head, and now the server CPU is where we will first see AMD's latest CPU architecture. Along with our first benchmarks of Venice, today also marks our first chance to evaluate the Zen 6 CPU architecture, which will drive many AMD products over the coming two years, from server chips like Venice and Verano to consumer desktops, laptops, and more. There is a lot to unpack with today's launch.
## AMD EPYC: Generation on Generation
| | EPYC 9004 | EPYC 9005 | EPYC 9006 (SP7) |
|---|---|---|---|
| Codename | Genoa | Turin | Venice |
| Microarchitecture | Zen 4 | Zen 5 | Zen 6 |
| Core Manufacturing | 5nm | 4nm/3nm | 2nm |
| Max Cores/Threads | 128/256 | 192/384 | 256/512 |
| Core Complex | 16 + 32MB | 16 + 32MB | 32 + 128MB |
| Memory Support | 12x DDR5-4800 | 12x DDR5-6400 | 16x DDR5-8000 / MRDIMM-12800 |
| Memory Capacity | 6TB | 6TB | 8TB |
| PCIe (1P) | 5.0 x128 | 5.0 x128 | 6.0 x96 |
| Socket | SP5 | SP5 | SP7 |
| Peak Power | 400W | 500W | 600W |
With so much to do and so little time to do it, we are going to have a lot more content to follow. To get things started, for today's launch piece we are running the flagship EPYC 9996 through not only our agentic-workload-focused AgentSTH V7 benchmark suite, but also bits and pieces of what is essentially a preview of 2027's AgentSTH V8. For some context, we went back roughly a decade in server architectures, not just blindly picking up benchmark suites, but profiling workloads on dozens of platforms for inclusion in the suite.
We have lots of numbers for this one and some neat comparison points. The headline feature is that we now get up to 256 cores per socket, a new PCIe Gen6 I/O subsystem, and more than twice the memory bandwidth, along with a revised Zen 6 microarchitecture and SoC design. AMD is also splitting its lineup into multiple families for different applications, with two primary sockets, a return of the -X high-cache parts with Venice-X, and the LPDDR5X Verano. The new series covers a lot more ground and is by far the most ambitious innovation in the EPYC line since the switch to an I/O die, which allowed the EPYC 7002 to deliver a knockout. This is the Knockout Part Deux.
I also want to recognize Ryan, Sam, and Vic for helping us turn this around quickly. Ryan will cover the Zen 6 microarchitecture and SoC portion before I take back over on performance. Regular STH readers may have noticed that many of our pieces are much longer than they used to be, and doing these reviews has become a team effort.
## AMD EPYC 9006 "Venice": The Story So Far
Over the summer, AMD held a proper unveiling for its EPYC 9006 "Venice" server CPU platform at the company's annual Advancing AI event. That event has become AMD's marquee event of the year, a reflection of the importance of server parts to the company's bottom line. There, AMD laid out an aggressive plan for 2026 and beyond. Spearheaded by the Venice CPU platform, AMD aims not only to deliver its most powerful and most capable server platform to date, but to iterate on it over the next year or so to build a broad portfolio of server chips covering everything from rank-and-file servers to mighty HPC systems, and of course many AI nodes.
Now in its sixth generation of Zen-architecture server chips, Venice is in some respects AMD's most aggressive design yet. AMD is making heavier use of chiplets than ever before, and it now relies on advanced packaging techniques to tie them together. This has allowed AMD to fully leverage TSMC's N2 (2nm) process node, the company's first GAAFET-based node. AMD is using it to devote more transistors than ever to the Zen CPU cores to boost performance, and to pack in more CPU cores than ever before.
For high-throughput workloads, the highlight of Venice is up to 256 CPU cores in a single socket, a 33% improvement over EPYC 9005 "Turin" only a generation ago, with 20% higher IPC and higher clock speeds on top of that. For workloads where single-threaded performance and latency are more critical, AMD is bringing the 5.3GHz EPYC 9686F to market to double down on Zen 6's IPC improvements, with the highest clock speeds yet for an EPYC server chip.
AMD is keen to tap into the agentic era of computing, and there are many improvements in Venice and the Zen 6 CPU architecture that will help it get there. But do not underestimate the chip in other areas. AMD has invested in features such as PCIe Gen6 and new virtualization and security features, and it has even acquired a software engineering firm in recent months to develop software that replaces DRAM with flash memory. AI is certainly the highlight of the Venice story, but it is not the only story.
With any luck, AMD expects that over the next 12 months it will finally capture leadership of the server CPU market. As we saw in AMD's earnings last week, the company's data center division is already projecting that its revenues will surpass Intel's in Q4 of this year. AMD already holds 46% of the x86 server CPU revenue share, and the company seems confident that Venice will push it above 50% for the first time.
## EPYC 9006 SP7 Product Stack: Venice HF Gets a Spec Bump
Alongside its initial summer announcement of the EPYC 9006 lineup, AMD also published the complete specifications for its full stack of chip SKUs. These covered both the high-end SP7 platform launching today and the more restrained SP8 platform launching early next year.
As it turns out, AMD was sandbagging things a bit. Its flagship high-frequency chip, the EPYC 9686F, was originally announced with a peak frequency of 5.0GHz. That is no longer the case. The 9686F is now a 5.3GHz chip, a notable improvement just ahead of the hardware's launch and, admittedly, a point of pride (or at least bragging rights) for AMD.
In talking with AMD, the company found that the final silicon for its big Zen 6 CCD turned out even better than expected. Consequently, the earlier SKU stack was a bit conservative, and AMD can do better than 5.0GHz, allowing the fastest Venice to clock higher than the fastest Turin after all.
Here is what the final, shipping SP7 chip stack looks like:
| Model | CPU Cores | Threads | Max Boost Clock | Base Clock | L3 Cache | TDP |
|---|---|---|---|---|---|---|
| AMD EPYC 9996 | 256 | 512 | 4.1 GHz | 2.55 GHz | 1024 MB | 600W |
| AMD EPYC 9966 | 192 | 384 | 4.0 GHz | 2.9 GHz | 768 MB | 600W |
| AMD EPYC 9846 | 168 | 336 | 3.7 GHz | 2.85 GHz | 768 MB | 500W |
| AMD EPYC 9756 | 128 | 256 | 4.0 GHz | 3.15 GHz | 512 MB | 500W |
| AMD EPYC 9G76 | 96 | 192 | 4.8 GHz | 3.4 GHz | 384 MB | 500W |
| AMD EPYC 9656 | 96 | 192 | 3.7 GHz | 3.05 GHz | 512 MB | 400W |
| AMD EPYC 9686F | 96 | 192 | 5.3 GHz | 3.4 GHz | 384 MB | 500W |
| AMD EPYC 9556 | 64 | 128 | 4.3 GHz | 2.75 GHz | 384 MB | 300W |
| AMD EPYC 9586F | 64 | 128 | 5.3 GHz | 3.75 GHz | 384 MB | 500W |
Only the EPYC 9686F receives a specification bump. The rest of the lineup is unchanged from before. Notably, this means the 64-core EPYC 9586F does not share in the gains. Customers who want AMD's highest-clocked Venice chip will need to buy the 96-core version.