AMD is winding up Zen 6 cores for faster clock speeds, with chips reaching up to 256 cores, 5.3 GHz clocks and IPC gains of 20 to 31 percent, though not all of these features are on the same SKU.

After teasing its 256-core Epycs for more than a year, AMD is finally ready to talk about the architectural changes to the Zen core that make them possible. These changes will eventually power the next generation of Ryzen processors for desktop and mobile PCs.

During a press event in Las Vegas last week, AMD revealed details of its latest Zen cores, which promise an average 27 percent uplift in instructions per clock (IPC) across a variety of AI and server workloads, along with boosted clocks ranging from 4.1 to 5.3 GHz. We expect even higher frequencies on consumer chips before long, but AMD isn't ready to talk about Ryzen just yet.

CPU performance is a function of power, IPC, and clocks. With gains across all three, the cores are shaping up to be one of the company's biggest generational jumps ever.

**A tale of two cores**

As in past Epyc launches, Zen 6 isn't one core. It comes in two flavors: a frequency-optimized variant (Zen 6) and a density-optimized version (Zen 6c).

This split dates back to the launch of AMD's Bergamo Epycs in 2023, which packed 128 compact Zen 4c cores into just eight chiplets. The chip's debut drew comparisons to Intel's relatively new Efficient cores (E-cores), for obvious reasons. Under the hood, however, AMD's Zen 4c was nothing like Intel's approach. The core was nearly identical to Zen 4; it simply traded clocks and a bit of cache per core for a more densely packed CPU die.

The only difference between running an application on Bergamo or Genoa was how quickly it executed. The same could not be said of Intel's P- and E-cores, which use different ISAs.

This remained a defining characteristic and advantage of AMD's compact core architecture through Zen 5, which allowed it to ship Turin parts with up to 192 cores without users having to worry about whether their app was running on a compact core.

With Zen 6c, at least as we understand it, this philosophy is largely unchanged. Zen 6 and Zen 6c share the same ISA, with clock speed as the main differentiator. There are other microarchitectural differences between the two cores, designed to balance IPC and clock speeds more effectively.

Looking at the core's block diagram, this isn't immediately obvious. Zen 6 and Zen 5 share a very similar front end and back end.

We'd be tempted to call the core iterative if it weren't for the 20 to 31 percent IPC uplift for cloud and AI workloads that AMD claims over Zen 5. This suggests that, core for core, a 4.1 GHz Zen 6c-based Venice Epyc should deliver performance on par with a Zen 5-based Turin Epyc running at 5 GHz.

That's a sizable jump, but just because AMD sees generational gains in enterprise server and cloud workloads doesn't mean the same gains will appear on the client side. Many will recall the roughly 5 percent performance gains PC gaming enthusiasts reported with the Ryzen 9000 series, which led to the unfortunate turn of phrase "Zen 5 percent." That happened because game engines at the time simply weren't CPU-bottlenecked, so faster cores could only raise the ceiling so much. Even so, AMD fellow and "Zen daddy" Mike Clark told El Reg that PC buyers expect more than a 6 percent gain from Zen 6.

We're glossing over a number of low-level architectural optimizations here, but according to Clark, one of the biggest drivers of performance was the front end. Zen 5 introduced a dual front end, which worked well for simple workloads but lost much of its effectiveness under more dynamic loads.

"The Zen 6 team did a really good job for those larger footprint workloads that have a bipolar nature," Clark said. "It's not something that comes through. You're not going to see it in a block diagram very well. It's sort of subtle... but it's a big lever."

Another contributor was the move to a distributed scheduler in the out-of-order pipeline. One of the biggest performance drivers in modern CPU cores is that they don't execute instructions in the order received. Instead, they reorder instructions to keep the backend execution units fed with a constant stream of work.

This is where the biggest difference between Zen 6 and Zen 6c emerges. To account for the slower clocks on the latter, AMD gave Zen 6c's scheduler deeper queues, which Clark says helps with higher-latency workloads. Meanwhile, from what we understand, Zen 6's shallower queue lets it clock higher on less power.

Finally, AMD made several subtle changes to the backend that should have major implications for vector-heavy workloads, including AI. One of the more significant is the ability to perform four AVX2 or two AVX-512 loads per cycle.

While this doesn't improve AVX-512 performance much, applications that haven't been updated to use AVX-512 can now benefit from twice as many loads, which should improve throughput for legacy software. This should be useful on PCs in particular, where Intel's lack of AVX-512 support has made AVX2 the lowest common denominator for much software.

That's not to say AVX-512 didn't get attention this generation. For those running AI workloads on CPUs, Zen 6 now natively supports FP16 datatypes. Previously, FP16 was supported but required padding the data to FP32, which meant the lower precision bought little in performance. That's no longer the case with Zen 6.

On the topic of AI acceleration, Clark notes that Zen 6 doubled the VNNI-INT8 pipes from two to four, which should effectively double throughput for workloads that support them.

**Feeding the beast**

While not strictly part of the core, AMD's Zen 6 processors also address one of the biggest asymmetries associated with its frequency- and density-optimized cores.

Going back to Bergamo, choosing a density-optimized Epyc came at the expense of cache as well as clocks. Each Zen 4c or Zen 5c chiplet contained twice as many cores but the same amount of L3 cache.

With Zen 6 and Zen 6c, you may give up some clock speed, but cache per core is now a constant 4 MB. As we discussed in a Venice deep dive in September, each of the processor's eight CPU dies contains 12 or 32 cores, with 48 MB or 128 MB of L3 cache respectively.

The benefit is that users don't have to worry about different ISAs or cache hierarchies when optimizing their software stacks for AMD's Epyc processors. The same cannot be said of Intel's Xeon processors.

As noted earlier, Intel's performance and efficiency cores use different microarchitectures, ISAs, cache hierarchies, clocks, and even cluster their cores differently. This can cause real headaches for workloads that take advantage of wide vector registers like AVX-512, or accelerators like AMX, which run on Intel's P-cores but not on its E-cores.

This, along with support for SMT (Hyperthreading), which Intel has dropped for now, could help the House of Zen win even more market share from its longtime rival.