삼성전자와 TSMC는 인텔과 함께 ASML의 최신 리소그래피 장비를 도입하여 글로벌 AI 칩 부족 사태를 완화하고 첨단 패키징 역량을 확보할 계획이다.
Producing hardware capable of powering modern AI demands exceptionally complex machinery. In response, the industry’s leading technology firms are making substantial investments to maintain their competitive edge. Samsung and TSMC have officially committed to purchasing ASML’s advanced High-NA extreme ultraviolet (EUV) lithography systems.
This commitment aligns the world’s top contract manufacturers with Intel’s technological trajectory. Intel has already advanced its position by processing over one million wafers on its 18A process node for upcoming Panther Lake chips, while simultaneously testing an enhanced 18A-P variant for Apple. At $400 million per unit, each High-NA system represents a significant capital investment. Securing commitments from both Asian tech giants solidifies ASML’s hardware leadership as AI workloads continue to drive demand for unprecedented computational capacity.
Despite broad consensus that High-NA lithography represents the industry’s future, Samsung and TSMC plan to integrate these systems into their fabrication facilities according to distinct roadmaps for memory chips and custom processors.
Samsung aims to deploy the equipment by 2028, targeting high-density DRAM production. Samsung CEO Young Hyun Jun stated, “etching finer circuit lines into memory chips reduces manufacturing headaches and keeps silicon scaling going strong across both memory and foundry operations.”
TSMC is pursuing a longer-term deployment schedule, with a planned rollout in 2030. Bolstered by sustained AI-driven demand that drove July revenue to NT$467.58 billion, TSMC has increased its annual capital expenditure forecast to between $60 billion and $64 billion. CEO Dr. C.C. Wei noted, “as AI chips grow more complex, foundries will have no choice but to rely heavily on High NA tools for more layers of silicon.” Meanwhile, memory competitor SK Hynix is evaluating participation within the same 2028 timeframe.
Acquiring next-generation lithography equipment is only part of the challenge; manufacturers must also transition away from legacy 6-inch photomasks to resolve critical stitching limitations. To maximize the capabilities of these systems, ASML, TSMC, Samsung, and Intel are collaborating to fundamentally redesign photomasks—the light-transmitting templates used to pattern circuits onto silicon wafers.
Historically, semiconductor manufacturers have standardized on 6-inch photomasks. However, High-NA optics reduce the projection field by half. Fabricating large AI chips measuring 800mm² requires manufacturers to “stitch” multiple exposure fields together, introducing alignment seams, elevating defect rates, and increasing production costs.
To address these limitations, the consortium is transitioning to a new 12-inch mask standard. ASML Chief Technology Officer Marco Pieters observed, “larger masks remove stitching bottlenecks entirely while boosting scanner output by 40%.” A pilot production line is scheduled to begin testing in 2031, establishing the foundation for full-scale commercial manufacturing by 2033.