반도체·하드웨어 · 리포트

화웨이는 차세대 어센드 NPU를 몇 분기 내에 출시하는 AI 가속기 로드맵을 공개했으며, 어센드 960PR은 예상 FP4 성능의 두 배를 달성할 것으로 보인다.

중국 내 실리콘 경쟁 가속화가 엔비디아에 대한 압박으로 작용하며, 초거대 클라우드 기업들이 가속기 조달처와 HBM/파운드리 용량 계획을 다각화하도록 유도하고 있다.

업계 전문지Slicast · 2026년 9월 18일 10:30 UTC · 글로벌 · 출처: Tom's Hardware

중요도 85

At its annual Huawei Connect event, Huawei unveiled an updated AI hardware roadmap featuring new accelerators, supporting processors, and an accelerated timeline for next-generation Ascend 960 chips. The company also disclosed specifications for the Ascend 970 and 980, introduced the Peerium architecture built on UnifiedBus, and expanded its vertically integrated AI infrastructure portfolio.

Huawei is currently transitioning from the SIMD architecture it has relied on for nearly a decade to a new SIMD+SIMT design. The company refers to its accelerators as neural processing units (NPUs). The updated architecture combines vector-based processing with thread-level parallelism to enhance hardware utilization and performance across diverse AI workloads, leveraging SIMD for data-parallel operations and SIMT for branch-heavy tasks.

The first NPUs to implement this new architecture are the Ascend 950PR, designed for prefill and recommendation workloads, and the Ascend 950DT, targeted at decoding and training. During the event, Huawei noted that the Ascend 950 platform is gaining traction, with Atlas 950 SuperPoD systems reportedly entering large-scale commercial deployment, though specific details were withheld. Testing of the training-focused Ascend 950DT has yielded positive results, and the company anticipates that multiple Chinese AI developers will begin training models on 950DT-based systems next year. However, Huawei acknowledged that current manufacturing capacity remains insufficient to meet domestic demand.

In September 2025, Huawei announced a maximum Atlas 950 SuperPoD configuration featuring 2,048 Kunpeng 950 CPUs, 8,192 Ascend 950DT NPUs, 160 cabinets (128 compute and 32 communications nodes), delivering 8 FP8 EFLOPS, 16 FP4 EFLOPS, and 16 PB/s of aggregate interconnect bandwidth. By July 2026, however, Huawei publicly demonstrated a deployed system containing only 256 CPUs and 1,024 accelerator cards—significantly below the stated maximum. Although the architecture is still described as scalable to 8,192 NPUs, this upper limit has been removed from Huawei’s public website, leaving the exact status of large-scale commercial deployments unclear.

Adoption of the Atlas 950 SuperPod appears to be progressing slowly, likely due to supply constraints or the substantial software redesign required to support the new architecture. Regardless, the platform serves primarily as a stepping stone, allowing Huawei to refine its ecosystem ahead of the more advanced Ascend 960 series and subsequent generations.

The Ascend 960 family will launch with the Ascend 960DT in Q1 2027, marking a formal release three quarters ahead of the previous schedule. The Ascend 960DT is expected to deliver 2 FP8 PFLOPS and 4 FP4 PFLOPS, equipped with 288 GB of HiZQ memory offering 9.6 TB/s of bandwidth and a 2.2 TB/s interconnect.

The Ascend 960PR will follow in Q3 2027, arriving one quarter ahead of schedule. It delivers 2 FP8 PFLOPS for training and 8 FP4 PFLOPS for inference—double the figure Huawei projected last year. The chip includes 192 GB of memory with 2.4 TB/s of bandwidth and maintains the 2.2 TB/s interconnect. For context, NVIDIA’s VR200 GPU, slated for Q4 2026, is expected to deliver 35 NVFP4 PFLOPS for training and 50 NVFP4 PFLOPS for inference, backed by 288 GB of HBM4 memory.

“We are evolving our Ascend chip series on a one-generation-a-year cycle,” said David Wang, the Deputy Chairman of the Board and Rotating Chairman at Huawei, in his keynote. “In 2028 and 2029, we will roll out the Ascend 970 and 980 chips, respectively. Thanks to the Tau (τ) Scaling Law, not only will their compute specifications continue to double, but you can also expect to see huge improvements across the board in terms of memory bandwidth, memory capacity, interconnect bandwidth, and more.”

|---|---|---|---|---|---|---|---|

| Ascend 910C | 2025 Q1 | SIMD | – | – | 128 GB | 3.2 TB/s | 784 GB/s | FP32, HF32, FP16, BF16, INT8 |

| Ascend 960DT | 2027 Q1 | SIMD + SIMT | 2 PFLOPS | 4 PFLOPS | 288 GB | 9.6 TB/s | 2.2 TB/s | FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, HiF4 |

| Ascend 960PR | 2027 Q3 | SIMD + SIMT | 2 PFLOPS | 8 PFLOPS | 192 GB | 2.4 TB/s | 2.2 TB/s | FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, HiF4 |

| Ascend 970 | 2028 | SIMD + SIMT | 3.6 PFLOPS | 14 PFLOPS | 288 GB | 14.4 TB/s | 4.4 TB/s | FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, HiF4 |

| Ascend 980 | 2029 | SIMD + SIMT | 7.2 PFLOPS* | 28 PFLOPS* | 384 GB | 38.4 TB/s* | 8 TB/s* | FP32, HF32, FP16, BF16, FP8, MXFP8, HiF8, MXFP4, HiF4* |

Beginning with the Ascend 960 series, Huawei intends to maintain a one-generation-per-year release cadence for its AI accelerators. Advancing the Ascend 960DT by several quarters represents a significant milestone. More notably, Huawei has doubled the FP4 performance of the Ascend 960PR relative to initial projections, indicating a substantial redesign of the chip’s low-precision compute logic rather than simple adjustments to memory or clock speeds. This trend will continue, with a fourfold ratio between FP4 and FP8 performance becoming a defining characteristic of both the Ascend 970 and 980.

The Ascend 970, scheduled for 2028, will deliver 3.6 FP8 PFLOPS and 14 FP4 PFLOPS, supported by 288 GB of memory at 14.4 TB/s bandwidth and a 4.4 TB/s interconnect. The Ascend 980 will follow in 2029 with 7.2 FP8 PFLOPS and 28 FP4 PFLOPS, paired with 384 GB of memory offering 38.4 TB/s bandwidth and an 8 TB/s interconnect. Huawei notes that the Ascend 980 specifications remain preliminary.

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