화웨이는 차세대 Ascend 960DT NPU를 조기 출시할 계획이며, 이를 중국 내 최고 수준의 국산 가속기 대체재로 포지셔닝하고 있다.

At its annual Connect conference, Huawei unveiled a new generation of AI accelerators engineered to outperform any Nvidia hardware currently available in China. The release presents a strategic advantage for domestic developers who have historically relied on less capable local alternatives. Codenamed the Ascend 960DT—where “DT” denotes decode and training—the chip is scheduled to launch in Q1 2027, arriving three quarters ahead of its initial projection. Featuring up to 288 GB of Huawei’s custom HiZQ memory, a domestic alternative to global high-bandwidth memory standards, and up to 4 petaFLOPS of FP4 performance (halved at FP8), the 960DT delivers double the performance and memory capacity of the company’s 950-series accelerators introduced earlier this year.

In direct comparison with American GPUs, the 960DT matches Nvidia’s B300 series in memory capacity and bandwidth, though it delivers approximately half the FP8 and one-third the FP4 compute performance. While this marks a substantial advancement for Huawei, it remains behind global leaders such as Nvidia’s Rubin and AMD’s newly released MI455X, both of which offer significantly higher compute throughput and memory bandwidth. Rubin alone provides between 35 and 50 petaFLOPS of FP4 performance, 288 GB of HBM4 memory, and 22 TB/s of bandwidth, placing it in a different performance tier. Nevertheless, neither chip is legally available in China, leaving domestic developers without superior alternatives. Currently, the highest-tier Nvidia GPU permitted for sale in China offers comparable dense floating-point performance, double the memory capacity, double the memory bandwidth, and support for larger scale-up configurations.

The performance gap may be less critical than it appears, as modern AI models are rarely trained or deployed on single GPUs or NPUs. Platform scalability has become the defining metric. Leading competitors like Nvidia and AMD currently deploy 72 GPUs per rack-scale compute platform, expandable to 576 units via optical interconnects for scale-up and scale-out networking. Huawei plans to follow a similar architecture with its 960-series accelerators, utilizing near-packaged optics (NPO) to scale compute domains across up to 4,096 chips, delivering up to 16 exaFLOPS of FP4 compute. Where Huawei trails in raw compute density, it compensates through massive scale—a strategy previously demonstrated by Google’s TPU clusters. Given Huawei’s historical strength in high-speed networking, this approach is logical. NPO technology resolves key scaling bottlenecks and reliability issues associated with earlier Huawei designs, where pluggable optics were power-intensive, failure-prone, and space-consuming. By consolidating 48,000 800 Gbps pluggable optics into 5,500 Hi-One NPO units, Huawei reports a 550-kilowatt reduction in power consumption and a 50% decrease in failure rates. The company states the new architecture enables 99.8% system uptime. This reliability improvement is particularly relevant for Chinese model developers facing regulatory and supply-chain pressures to transition from Western hardware. Notably, DeepSeek previously encountered training limitations with earlier Huawei NPUs and reverted to Nvidia GPUs.

Alongside the high-bandwidth 960DT, Huawei is developing a compute-optimized variant, the Ascend 960PR, scheduled for Q3 2027. The 960PR serves a function analogous to Nvidia’s canceled Rubin CPX accelerators. The “PR” designation indicates a focus on prefill operations and recommendation workloads, with Huawei trading memory capacity and bandwidth for significantly higher low-precision compute throughput. The PR variant will deliver up to 8 petaFLOPS of FP4 performance, paired with 192 GB of custom HiBL memory providing 2.4 TB/s of bandwidth. Designed to operate alongside the DT chips, the 960PR aims to enhance large language model inference. During the inference pipeline, the compute-intensive prefill stage—which processes input prompts—is delegated to the 960PR, while the memory-bound decode stage—which generates output tokens—runs on the 960DT. This heterogeneous architecture has demonstrated strong performance gains, mirroring configurations seen in Nvidia’s Vera Rubin lineup and Groq’s LPX systems. However, Huawei currently lacks a dedicated SRAM-heavy decode accelerator to fully match these implementations.

At Connect, Huawei outlined ambitions to scale its compute infrastructure to clusters exceeding 500,000 NPUs. In a recent proof of concept, the company successfully expanded its Ascend 950-based TaiShan superpod to 4,096 accelerators. Leveraging a two-tier, four-plane Clos network topology, Huawei anticipates supporting clusters of up to 512,000 NPUs in the near term, with multi-rail topologies potentially enabling million-NPU superclusters. These figures remain theoretical and have not yet been validated in production environments.

Looking ahead, Huawei previewed its next two Ascend generations, projecting consistent performance improvements, expanded memory, and accelerated interconnects. The Ascend 970-series, expected around 2028, will deliver up to 3.6 petaFLOPS of FP8 or 14 petaFLOPS of FP4 performance. This shift toward lower-precision compute aligns with industry trends observed in AMD and Nvidia’s latest architectures. Memory capacity will remain at 288 GB, but bandwidth is projected to reach 14.4 TB/s, significantly benefiting AI inference workloads. By 2029, Huawei targets a doubling of performance to 7.2 petaFLOPS FP8 and 28 petaFLOPS FP4, alongside memory expansion to 384 GB and bandwidth scaling to 38.4 TB/s. Given the extended timeline, these roadmaps remain subject to revision as development progresses.