At Hot Chips 2026, IBM unveils a 2nm-based mainframe processor featuring an 11-core design that natively runs both ARM and z/Architecture instructions at a 5.7 GHz base frequency.

At Hot Chips 2026, IBM unveiled its next-generation AI processor, marking the first time the company has supported dual-ISA execution natively within a single core. Born from a collaboration between IBM and Arm announced in April, the chip is designed to bring the extensive software ecosystem of Arm to IBM’s mainframes. This enables businesses to unify their deployments instead of relying on separate Arm/x86 servers and z/Architecture mainframes for different workloads. Rather than employing a heterogeneous CPU with separate Arm and z/Architecture cores on the same die, IBM engineered a single core capable of executing either instruction set architecture and dynamically switching between them “within nanoseconds.” During the reveal, IBM stated that this approach treats both ISAs as “first-class citizens.”

To support AArch64 instructions, IBM utilizes the Linux Kernel-based Virtual Machine (KVM) framework—the same mechanism that enables Linux on Z mainframes—while standard z/Architecture instructions bypass KVM entirely. This design ensures that mainframe reliability remains uncompromised despite broader software compatibility. IBM claims the system achieves 99.999999% uptime, equating to merely 0.032 seconds of downtime per year. Historically, much of modern software development, particularly in AI, targets x86 or Arm architectures, leaving mainframes to develop independent solutions. While IBM has previously ported software to s390x, that strategy lacks long-term scalability. “We would never be able to work with all of them,” Tina Tarquinio, chief product officer at IBM for IBM Z and LinuxONE, told VentureBeat. The new dual-ISA core executes Arm software without modification, allowing Arm-based virtual machines to run as if on native Arm silicon—because, architecturally, they effectively are.

The processor, which will presumably power the upcoming z18 mainframe, features 11 high-performance cores built on a 2nm process node, each operating at a 5.7 GHz base frequency. Even disregarding the dual-ISA capability, these specifications represent a significant leap over IBM’s current Telum II processor, introduced in 2024. The Telum II comprises eight cores running at up to 5.5 GHz. Beyond core count and clock speed, the new chip retains the 36 MB of private L2 cache found in its predecessor but expands the virtualized caches to 432 MB of virtual L3 and 3.5 GB of virtual L4. Additional features carried forward include an on-chip data processing unit (DPU) and dedicated hardware accelerators for AI, compression, and cryptography workloads. The core also supports simultaneous multithreading, available to both ISAs.

Alongside the main processor, IBM showcased its next-generation AI accelerator at Hot Chips 2026, a substantial upgrade over the current Spyre accelerator. The new unit features 16 cores optimized for emerging AI data formats, including FP4 and MXFP4. The most notable architectural shift involves memory: IBM has transitioned from LPDDR5 to HBM3e, sacrificing capacity for dramatically higher bandwidth. Each accelerator is equipped with 96 GB of HBM3e, delivering up to 4 TB/s of bandwidth—a 20x increase over what IBM achieved with LPDDR5.

Supporting native AArch64 execution required extensive modifications within the core itself. The chip includes a full hardware implementation of AArch64 v9.3 with Scalable Vector Extension (SVE) support, encompassing 2,792 AArch64 instructions. Starting at the top of the pipeline, the branch prediction unit retains the existing Telum II design without alteration. In the fetch engine, IBM leverages virtual cache tags to accelerate data retrieval while avoiding translation overhead. Decoding AArch64 instructions represents the largest area of silicon expansion in the core; IBM developed automation tools to parse ARM XML specifications and route instructions efficiently. During dispatch, general-purpose register renaming was repurposed using banked registers 16 through 31. In the arithmetic and load/store units, major data flows remain shared—“addition is addition,” as IBM noted—but new hardware structures were added to handle SVE and specialized data types like FP16. IBM also identified non-obvious opportunities to reuse existing CISC logic, such as for memory copy and clear operations. Finally, the X-Late (translation) engine reuses the Translation Lookaside Buffer (TLB) but implements a new page-walk mechanism.

Unlike heterogeneous designs that mix ISAs across different cores, IBM’s dual-ISA core was driven by the need to deliver the scale of the Arm software ecosystem onto a mission-critical platform. Mainframes continue to serve as the backbone for vital data movement across financial institutions, governments, and other enterprise sectors. IBM typically releases new mainframe generations every two and a half to three years, following the 2024 Hot Chips unveiling of the z17. IBM expects this next-generation mainframe to follow a similar release cadence. As is customary with deep mainframe infrastructure, however, actual deployment timelines will largely depend on individual institutional requirements.