XCENA unveiled its MX1 architecture at Hot Chips 2026, which integrates memory expansion and near-memory computing to alleviate bandwidth bottlenecks.

XCENA unveiled its MX1 architecture at Hot Chips 2026, which integrates memory expansion and near-memory computing to alleviate bandwidth bottlenecks.

This approach directly addresses the memory wall for large language models, offering a viable path to sustain scaling without relying solely on HBM capacity constraints.