Samsung showcased the industry’s first LPDDR5X-PIM at Hot Chips 2026, embedding logic units directly into memory to achieve 3.01x faster speeds and 8x bandwidth for AI inference.

At Hot Chips 2026, Samsung unveiled the industry’s first LPDDR5X-PIM (Processing-in-Memory) module, integrating computational logic directly into low-power DRAM. Building on PIM technology initially demonstrated in 2021 through HBM stacks in AMD accelerators, the architecture places calculation units alongside DRAM cells to execute foundational operations locally. By handling these computations within the memory subsystem, Samsung eliminates processor bottlenecks, significantly accelerating AI inference workloads.

In preliminary benchmarks, Samsung reports that LPDDR5X-PIM delivers a 2.28x improvement in model run time and a 3.01x increase in tokens per second compared to standard LPDDR5X. The technology also achieves an eightfold bandwidth expansion. While LPDDR5X-9600 typically peaks at 76.8 GB/s, PIM integration raises effective bandwidth to 614 GB/s by minimizing data movement and retaining basic logic within the memory stack.

The strategic shift toward in-memory processing addresses critical cost and efficiency constraints in AI hardware. As Micron warned earlier at Hot Chips, HBM wafer demand continues to intensify. Memory already constitutes the majority of AI chip expenses, with its cost share steadily expanding. Coupled with the substantial power requirements of DDR5 and HBM, LPDDR5X presents an optimal target for PIM adoption. Samsung originally introduced HBM-PIM in 2023 alongside the LPDDR5X-PIM concept; the Hot Chips presentation marks the transition of the latter from prototype to validated product. The company is also advancing LPDDR6X-PIM, targeting an initial JEDEC specification later this year.

Samsung’s LPDDR5X-PIM architecture assigns a dedicated PIM unit to each memory bank, a structural improvement over HBM-PIM designs that required sacrificing banks to accommodate logic. Within each bank, the memory array, scale register file (SRF), and source register file feed parallel multiply-accumulate (MAC) trees. Computed outputs—whether integer or floating-point—are stored in a vector register file (VRF). To maintain compatibility with traditional DRAM controllers, the module operates in either single-bank (conventional DRAM) or multi-bank (PIM) mode. Samsung resolved conventional DRAM reordering limitations through Address Align Mode (AAM), which maps DRAM addresses to MAC instructions and assigns VRF/SRF addresses based on row/column addresses rather than an instruction register file.

During a demonstration of the data flow, Samsung outlined a MAC operation using pre-loaded weight parameters in multi-bank PIM mode. Fifty-one-two bytes of FP8 activation data were partitioned into sixteen 256-bit packets, written across the banks, and logged in the SRF. A PIMX_RD command retrieved weight data from the DRAM banks, feeding it into the MAC trees alongside SRF data. Upon completion, each operation’s output vector was written to the VRF. A subsequent PIMX_WR command transferred the results back to the DRAM banks. With a 1-kbit VRF capacity, up to four calculations could be stored simultaneously. Finally, the host system switched to single-bank mode and executed sixteen reads to retrieve the aggregated output.

Physically, LPDDR5X-PIM mirrors standard LPDDR5X packaging, utilizing a 561-ball array. Modules feature two 64-bit ranks and 16 GB capacity, built from eight dies total (four per rank). In testing, Samsung deployed an edge AI accelerator—potentially an early Gaia SoC—to run Llama 3.1 with 8 billion parameters. Attendees noted minor discrepancies in output precision, which Samsung attributed to ongoing optimization efforts. The company emphasized that while accuracy refinements continue, the performance advantages will remain intact.

Despite the added computational logic, Samsung maintains that overall power consumption will remain lower than conventional DRAM. Although peak power draw will be “much higher” due to the bursty nature of PIM operations, reducing redundant data transfers between the host and memory yields net energy savings. “We’re not having significant power increase,” stated Samsung’s Karam Hwang. Historically confined to consumer electronics, LPDDR5X has recently expanded into server and accelerator markets, notably powering Nvidia’s Vera CPU via SOCAMM2 modules and Intel’s Crescent Island AI accelerator. With PIM integration, Samsung targets server, client, and mobile segments, positioning LPDDR5X-PIM to accelerate edge AI workloads on portable devices and lower-tier accelerators like Crescent Island.