Samsung introduces 'zHBM' technology that stacks HBM directly on GPU packages, targeting AI compute bottleneck in memory bandwidth.
Samsung Electronics will unveil its next-generation 3D memory and storage roadmap at FMS (Future of Memory and Storage) 2026, aimed at resolving performance bottlenecks in AI systems. The centerpiece is zHBM technology, which vertically stacks HBM (High Bandwidth Memory) directly atop GPUs, delivering four times the data transfer speed of HBM4 while consuming only one-quarter of the power. In the NAND segment, z-NAND, designed to minimize latency, will be presented as the next-generation strategic product. SK Hynix is also entering the AI memory semiconductor race with its tiered memory system, signaling that competition is expanding from raw performance to architectural innovation.
The FMS 2026 conference—the world's largest memory and storage industry event—is being held over three days beginning August 4th at the Santa Clara Convention Center in California. Marking the event's 20th anniversary, this year's gathering is regarded as the largest assembly in the memory and storage industry. Lee Jin-yeop, Executive Vice President and Head of Flash Development at Samsung Electronics' Memory Business Unit, and Kim Kyung-ryun, Managing Director of the DRAM Development Office, will deliver keynote addresses.
A Samsung Electronics representative stated: "At FMS 2026, we will redefine AI systems through 3D memory and storage innovation. We plan to introduce next-generation HBM and V-NAND (vertical stacked NAND flash) technologies optimized for AI workloads." Industry observers widely expect zHBM—a next-generation HBM applying 3D stacking technology—to be unveiled for the first time at this event.
zHBM represents an entirely new memory architecture that stacks HBM vertically on top of GPUs. First revealed by Samsung Electronics on February 11 at SEMICON Korea 2026, the technology dramatically shortens data travel distances compared to conventional side-by-side GPU and HBM arrangements, simultaneously boosting bandwidth and power efficiency. Song Jae-hyuk, Chief Technology Officer of Samsung Electronics, emphasized at the time: "zHBM's data transfer speed is four times faster than HBM4 while consuming only one-quarter of the power. We will achieve another major innovation in bandwidth and power efficiency." Based on JEDEC's official HBM4 standard specifications announced in April 2025, which defines a maximum bandwidth of 2TB/s per stack, Samsung's cited 4x improvement would position zHBM at approximately 8TB/s per stack theoretical bandwidth.
In the NAND segment, z-NAND is being positioned as the next-generation strategic product. Previously, GPUs had to route through CPUs (Central Processing Units) and DRAM to access data stored on SSDs, inevitably introducing latency. z-NAND is focused on minimizing latency and enhancing input/output (I/O) performance to eliminate this bottleneck. At last year's FMS, Samsung announced it was developing z-NAND with the goal of achieving 15 times the processing performance of conventional NAND while reducing power consumption to one-fifth.
Industry observers view the 3D architecture as the next-generation solution to AI system bottlenecks. As data processing demand expands from generative AI to agentic AI and physical AI, reducing inter-chip data travel distances improves both bandwidth and power efficiency. An industry official explained: "As AI workloads evolve, the volume of data and context requiring processing grows exponentially, making it increasingly clear that conventional compute-centric architectures face limits in improving performance and power efficiency. 3D memory and storage technologies like zHBM and z-NAND represent an attempt to implement memory-centric AI infrastructure by reducing data movement between compute units and memory while simultaneously expanding performance and capacity."
SK Hynix is countering at FMS 2026 with a tiered memory system built on xPU (processing units), HBF (High Bandwidth Flash), and CXL (Compute Express Link). Kim Cheon-seong, Vice President and Head of the Solution Development Division at SK Hynix, and Kang Uk-seong, Vice President of Next-Generation Product Planning, will deliver a keynote on "Efficient AI Infrastructure Orchestration through Tiered Memory in the Agent AI Era."
HBF is a next-generation memory being developed by SK Hynix following a joint standardization kickoff event held on February 25 at SanDisk's headquarters in Milpitas, California, where a dedicated workstream was established under the OCP (Open Compute Project). The goal is to create a new storage tier between HBM and SSD, securing both the bandwidth and capacity required for large-scale AI inference services. SK Hynix's tiered architecture "IMTE (Inference Memory Tiering Expansion)" expands the existing "HBM→DRAM→SSD" memory hierarchy by adding CXL hybrid memory, resulting in an "HBM→DRAM→CXL memory→SSD" structure. In this design, CXL memory predicts which data HBM and DRAM will need and prefetches it from SSDs. According to Taiwan-based market research firm TrendForce, this architecture improves AI inference efficiency by 35.7% compared to conventional designs.
The next-generation memory and storage technologies unveiled by both companies around FMS 2026 demonstrate that competition in the AI semiconductor market is shifting from simple performance battles to system architecture innovation. As data movement bottlenecks between GPUs and memory emerge as the critical variable determining overall AI system performance, the technological capabilities of memory semiconductor companies have become a decisive factor in AI infrastructure success.