AMD Venice 256-core EPYC CPU announced with Zen 6: 1024 MB L3 cache, 16-channel memory, 5+ GHz clocks.

AMD is finally providing details on its first Zen 6 CPU after more than a year of teasing. The Epyc 9996 is a 256-core / 512-thread chip built on Zen 6 architecture and represents the flagship launch in what AMD describes as a "broad portfolio" for Venice. The company claims significant performance advantages over Nvidia's upcoming Vera and Intel's Xeon 6, and plans to build out the Venice range with purpose-built designs over the next year.

"It's not just a single processor," said AMD's Ravi Kuppuswany, corporate VP of compute and enterprise solutions. "It's a portfolio." The strategy mirrors how Intel has segmented its Xeon ranges and how AMD has softly differentiated its Epyc offerings, with solutions optimized for specific applications rather than a one-size-fits-all approach.

The main Venice lineup launches on the SP7 socket and scales up to 256 cores and 512 threads with 1.6 TB/s of memory bandwidth using fast MRDIMMs, and 128 PCIe 6 lanes in single-processor configuration (160 lanes in dual-processor). The 256-core configuration uses AMD's Zen 6c "dense" design. Standard Zen 6 Venice scales to 128 cores and 256 threads, while high-frequency variants max out at 96 cores.

Additional configurations are planned. Venice on the SP8 socket, launching in the first half of 2027, will offer as few as eight cores and up to 128 cores for smaller deployments, supporting eight-channel memory with two DIMMs per channel and the same 128 PCIe 6 lanes. Venice-X is expected in the second half of 2027 on the SP7 socket with 96 cores and up to 1,152 MB of stacked L3 cache, capable of clocking up to 5.15 GHz. Verano, arriving in the second half of 2027 on the SP8 socket, targets AI workloads with up to 72 cores and 5 GHz peak clocks, leveraging a 24-channel LPDDR5X memory system with SOCAMM2 modules.

Venice's memory architecture represents a significant upgrade. The SP7 configuration scales to 16-channel memory with MRDIMMs running at 12,800 MT/s or standard DDR5 RDIMMs at 8,000 MT/s—a substantial jump over Turin's 12-channel memory with RDIMMs at 6,400 MT/s. AMD claims per-socket bandwidth of 1.6 TB/s, significantly higher than Vera's 1.2 TB/s and nearly triple Turin's 576 GB/s per-socket bandwidth. Intel recently enabled 8,000 MT/s RDIMMs on select Granite Rapids and Clearwater Forest SKUs, with plans for MRDIMM support at up to 8,800 MT/s arriving in Q1 2027.

Zen 6 is built on TSMC's N2 process. AMD confirmed 32 cores per CCD alongside two IODs. The 256-core configuration includes 1,024 MB of L3 cache—nearly triple the Epyc 9965—with each CCD having access to 128 MB of L3, or 4 MB per core, double Turin's allocation. This is conventional cache, not stacked; that arrives with Venice-X.

AMD's benchmark results focus on agentic AI workloads, many of which apply to high-concurrency networking, code compilation, and media processing. Against the prior-generation Epyc 9965 (a 192-core Zen 5 dense design), the Epyc 9996 claims 1.2x improvement in front-end operations using NGINX and the WRK load generator. Compared to Intel's Xeon 6980P, gains reach 2.8x in the same test.

In data-heavy AI workloads measured by the TPCx-AI benchmark (AI use cases per minute), AMD claims 1.7x gen-on-gen improvement and 3.4x over the Xeon 6980P. Vectorized workloads using Meta's FAISS library show 1.6x gen-on-gen gains and 2.3x over Intel. For enterprise tools including TPC-H, TPC-C, and Redis, AMD reports 1.6x gen-on-gen improvement and 2.6x over Intel based on geomean throughput across multiple tests.

Direct agent testing using five different agent personas shows 1.5x gen-on-gen improvement and 2.5x over the Xeon 6980P. AMD ran direct comparisons against Nvidia's Vera using GNU 15.2 compiler with both systems at 600W TDP. In SPEC CPU 2026 throughput (SPECrate integer suite), the 256-core dense Venice design claims 2.2x improvement over Vera. The 96-core high-frequency Venice variant claims 1.2x per-core performance improvement compared to Vera. In SPEC CPU 2017 (SPECrate integer), Venice achieves 2x throughput compared to Intel's Xeon 6980P and 1.3x per-core performance versus Arm's new AGI.