Tenstorrent achieves production-ready AI processor SoC with advanced ASIC engineering.

INVECAS Inc and Tenstorrent Inc announced that Tenstorrent achieved first-pass silicon success for its Grayskull AI processor system-on-chip utilizing INVECAS's Advanced Chip Builder Tool (ACT) physical implementation flow to achieve predictable design convergence, best-in-class PPA, and accelerate time-to-tape-out for complex design. INVECAS provides ASIC design solutions across all technology nodes up to 6nm FINFET for key global customers targeting next generation AI, 5G, IoT, automobile and networking markets. The company's customers work with complex designs featuring multiple hierarchies with 1B-2B+ gate counts and large numbers of high-speed interfaces. INVECAS's Package and Test Design and Development team utilizes state-of-the-art simulation and design tools to achieve clean signal integrity and power integrity for complex high-power products, while its ATE Development team rapidly implements test vectors and test methodologies to ensure reliable first-pass silicon with industry-leading metrics for high quality and low DPPM during production.

Tenstorrent's Grayskull is a flagship AI processor featuring the company's proprietary conditional execution architecture for artificial intelligence, enabling inference and training computations to be tailored at run-time for each input presented to the model. The architecture comprises an array of Tensix cores, each containing a high utilization packet processor, high bandwidth local SRAM, a powerful programmable SIMD, and dense math computational block, along with five RISC processor cores. Grayskull is a 620mm² chip manufactured using Global Foundries' 12nm process, integrating 120 Tensix cores, a 4-core ARC CPU, eight channels of LPDDR4, 16 lanes of PCI-E Gen 4, and a proprietary high-performance NoC.

Drago Ignjatovic, VP of Silicon Engineering at Tenstorrent, stated: "Successfully completing a large, high frequency SoC design, with significant IP-level changes occurring until late in the project, required a combination of architectural and design flow innovation, as well as a high degree of trust and collaboration between the Tenstorrent and INVECAS teams. Tenstorrent's SoC Architecture, combined with INVECAS advanced physical implementation and DFT methodology, enabled a modular and efficient design flow, which in turn enabled us to continuously improve our core IP almost up to the point of tape-out."

Srinivasa Gutta, VP of engineering at INVECAS, explained that time to market is critical in the competitive semiconductor market, and that a complex design like Grayskull with 120 AI core engines in deep sub-micron technologies requires innovative approaches and close collaboration between SOC Architects and Physical Design Architects. He noted that "Flexible design methodology with ACT enabled independent design closure of blocks in parallel with abutted top level design style and drop in placement of newly developed AI core late in the design phase all the while ensuring predictable timing and IR convergence at full chip level." Gutta added that INVECAS's DFT architecture included top-level glue-less DFT logic with options to test and debug single AI cores or groups of AI cores in parallel to speed up test time, and achieved scan shift frequency of 150MHz+ with pipeline flops planned and pushed into blocks with zero top level impact.