TSMC expands outsourcing of advanced AI chip packaging (CoWoS) steps to third-party providers to alleviate persistent bottleneck.
Taiwan Semiconductor Manufacturing Co. (TSMC) is expanding its outsourcing of a critical step in the production of artificial intelligence chips, a strategic move intended to alleviate a persistent manufacturing bottleneck that has constrained the supply of AI accelerators.
According to industry sources, TSMC has decided to entrust additional volumes of the CoW (chip-on-wafer) packaging stage of its advanced CoWoS process to outsourced semiconductor assembly and test (OSAT) providers, including ASE Technology Holding. In response, major OSAT firms are placing equipment orders to build new production lines, with purchase order discussions reportedly underway with South Korean materials, parts, and equipment suppliers. While the scale of the investment has not been disclosed, it is expected to significantly boost existing production capacity.
CoWoS is TSMC's proprietary 2.5D packaging technology, essential for manufacturing AI chips. The process places a processor such as a graphics processing unit (GPU) at the center and surrounds it with high-bandwidth memory (HBM), using an interposer as a bridge to connect them. TSMC designates the step of attaching the chip to the interposer as CoW, while the bonding of the interposer to the main substrate is called WoS (wafer-on-substrate). Historically, TSMC has outsourced most of the WoS stage, licensing the technology to partners including ASE, Amkor Technology, and SPIL. While some CoW work has been contracted out previously, the volume was limited. This expansion marks a significant strategic shift.
The decision reflects relentless growth in demand for AI chips. With NVIDIA leading, global fabless chip designers and AI data center operators are increasingly developing and deploying their own silicon, creating demand that TSMC's internal capacity alone cannot satisfy. The company is estimated to control roughly 90% of the global AI chip manufacturing market.
"TSMC has continued to invest in packaging equipment for AI chip manufacturing, but it has been pointed out that a bottleneck still occurs at the packaging stage," said an industry official. "This expansion of outsourcing is an attempt to increase production capacity together with its key OSAT partners, as market demand continues to grow."
The increased OSAT investment is expected to benefit the backend equipment supply chain, with particular focus on wafer and interposer dicing and bonding processes. Multiple South Korean equipment industry sources indicate that supply discussions for CoW-related equipment are already underway in laser processing and bonding sectors.
This expansion occurs as TSMC races to ramp production of its most advanced nodes. The company is on track to hit a monthly production target of 100,000 wafers on its 2nm process by the end of 2026, driven by demand from customers including NVIDIA, AMD, and Broadcom. TSMC's 3nm production is expected to reach 180,000 wafers per month ahead of its Q4 2026 schedule. The 2nm process contributed 3% of the company's Q3 2026 revenue and has seen four times as many tapeouts compared to 3nm at the same stage.
The expansion of CoW outsourcing represents a strategic acknowledgment that the packaging stage, not just leading-edge lithography, is a critical chokepoint for AI chip supply. By leveraging OSAT partner capacity, TSMC aims to increase overall output more quickly than it could alone. For OSAT providers, this represents significant growth opportunity, as they take on a larger share of high-value packaging work. The move signals that AI demand remains robust enough to justify major capital expenditures across the supply chain, with positive implications for semiconductor equipment makers and materials suppliers.