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Alibaba’s TSMC-built 5nm RISC-V XuanTie C950 chip now natively runs the Qwen-3.8 27B model, demonstrating deep vertical integration.

Native execution of a large language model on custom RISC-V silicon validates Alibaba’s strategy to reduce reliance on foreign accelerators for inference workloads.
Trade pressSlicast · August 19, 2026 · US · Source: Google News
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Alibaba appears to be adopting NVIDIA’s established vertical integration strategy by delivering day-zero support for its highly capable Qwen-3.8 27B AI model on its bespoke RISC-V processor, the XuanTie C950. Notably, this model requires only 32GB of VRAM to operate.

Unveiled in March 2026, the XuanTie C950 is positioned as a RISC-V-based solution for edge AI. Rather than relying on traditional GPUs for AI workloads like conventional ASICs often do, the chip functions as a server-grade 64-bit RISC-V processor. It integrates 64 compute cores on a single silicon die, with scalable clock frequencies reaching 3.20GHz. Multiple clusters, each containing eight cores, are natively interconnected via high-speed AMBA CHI fabrics. To efficiently manage demanding AI tasks, matrix and vector acceleration engines are embedded directly into the architecture, removing the dependency on discrete GPUs.

The XuanTie C950 incorporates standard L1 caches, a flexible and highly configurable L2 cache, and supports an optional shared L3 cache to mitigate inter-core communication bottlenecks. Additionally, the chip employs hardware-level intelligent data prefetching algorithms that anticipate memory requests, loading data strings into the cache hierarchy before the execution engine actually needs them.

Highlighting these developments, the Alibaba T-Head Xuantie RISC-V team announced: “Alibaba T-Head's Xuantie RISC-V team announces Day 0 support for Qwen-3.8 model, especially the 27B one.Its 64-core C950 CPU (w/ RVV support) can decode at 30 tps w/ 1.9s TTFT.Xuantie family has wide series of RISC-V chips for different edge applications. Ali can now sell the… https://t.co/yF731bykS1 pic.twitter.com/qmHfiZBxpa”

This announcement underscores the chip’s core performance capabilities. With native day-zero support for the Qwen-3.8 27B model, the XuanTie C950 achieves decode speeds of 30 tokens per second and a Time To First Token (TTFT) of just 1.9 seconds.

For context, the Qwen-3.8 27B is a 27-billion-parameter open-weight AI model featuring coding capabilities comparable to Opus 4.5, yet lightweight enough to run on a single MacBook.

By integrating day-zero support for this model into the XuanTie C950, Alibaba aims to both deepen customer retention within its ecosystem and significantly expand its compute flexibility. The company can seamlessly pair the C950 with additional AI accelerators across its data centers to optimize inference workloads.

About the author: Writing is my one incontrovertible passion. Over the past six years, I have authored over 2,200 distinct articles on financial and tech-related topics, spanning nearly 1 million words. As a member of the Wccftech mobile team since 2025 and an alumnus of the University of Toronto’s Rotman Commerce Program, I bring nuance, in-depth knowledge, and a unique perspective to every topic that I cover. When I'm not writing, I'm traveling the world, exploring hidden confectionaries and restaurants as an aspiring food connoisseur.

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Alibaba’s TSMC-built 5nm RISC-V XuanTie C950… · Slicast