Electronic design automation leader Cadence wins DARPA contract to accelerate machine learning in chip design processes.

Cadence Design Systems, Inc. (NASDAQ: CDNS) was selected by the Defense Advanced Research Projects Agency (DARPA) to support the Intelligent Design of Electronic Assets (IDEA) program, announced July 24, 2018. IDEA is one of six new programs within DARPA's Electronics Resurgence Initiative (ERI), designed to use advanced machine learning techniques to develop a unified platform for a fully integrated, intelligent design flow for systems on chip (SoCs), systems in package (SiPs) and printed circuit boards (PCBs). The ERI investments represent the next steps in creating a more automated electronics design capability that will benefit the aerospace/defense ecosystem and the electronic industry's commercial needs.

To fulfill the program charter over the four-year term of the contract, Cadence created the Machine learning-driven Automatic Generation of Electronic Systems Through Intelligent Collaboration (MAGESTIC) research and development program. This program will create a foundation for system design enablement by introducing greater autonomy within the design process and developing truly design-intent-driven products. The Cadence-led team includes Carnegie Mellon University and NVIDIA, two of the most renowned machine learning leaders in the world.

"We've been leading the industry in the development, deployment and support of electronic design flows that use machine learning, analytics and optimization technologies. This program will accelerate our roadmap toward realizing intelligent design flows for the next big leap in design productivity," stated Anirudh Devgan, president of Cadence. "This program will set the stage for enhancing the entire span of our analog, digital, verification, package and PCB EDA technologies, providing our customers with the most advanced system design enablement solutions."

The DARPA ERI programs address impending engineering and economics challenges that could disrupt the relentless half-century run of progress in microelectronics technology. The design work and fabrication required to keep pace in microelectronics is becoming increasingly difficult and expensive. The MAGESTIC program aims to advance the state of the art in machine learning to develop algorithms that optimize performance, extend support for advanced CMOS process nodes including 7nm and below as well as larger process nodes, automate the routing and tuning of devices to improve reliability, circuit performance and resilience, demonstrate improved power, performance and area (PPA) utilizing machine learning analytics and optimization, and stage the introductions of the technology, allowing the system to learn from users and allowing users to gain an understanding of how to best leverage the tools to achieve desired results.

The program will also extend Cadence's work in employing cloud-based design systems to handle large-scale distributed processing to speed design efforts.