Samsung debuts advanced 3D HBM and flash memory technologies designed for AI workloads, competing with SK Hynix and Micron in the memory race.

At the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, California, Samsung unveiled three next-generation memory technologies designed to address the growing bandwidth and storage demands of AI datacenters.

Samsung, a South Korean conglomerate with semiconductor operations including CMOS image sensors, logic devices, and memory products, is the world's largest memory supplier. The company also operates a foundry unit competing against TSMC and Intel.

**zHBM: Stacked High Bandwidth Memory**

Currently, high bandwidth memory (HBM)—widely used in AI applications—is incorporated into packages alongside AI chips in a 2.5D configuration, with the AI processor and HBM memory stack positioned side-by-side on an interposer. HBM typically vertically stacks 8, 12, or 16 DRAM dies connected via through-silicon vias (TSVs), employing a 1024-bit memory bus to enable high bandwidth transfer between memory and processor.

However, hyperscalers operating AI datacenters demand greater memory bandwidth to handle increasing AI complexity. Samsung's new zHBM technology addresses this by vertically stacking HBM directly atop the AI accelerator chip, minimizing the distance data must travel. Initially stacking one to four DRAM dies on the AI chip, "zHBM is designed to deliver higher bandwidth and improved power efficiency, enabling the ultra-fast data processing required for large-scale AI training and inference," according to Samsung. Targeted for 2029, zHBM is expected to deliver approximately eight times the performance of HBM5 and more than 10 times the memory density of HBM5 using next-generation wafer bonding technology.

**zNAND-O: High-Bandwidth Flash**

SK hynix and Sandisk have been developing high bandwidth flash (HBF), which vertically stacks NAND dies on an interposer to fill the memory gap between HBM and solid-state drives. Samsung's entry, zNAND-O, is a next-generation NAND architecture built on 3D NAND technology. While similar to HBF in using TSVs and UCIe interface, "the fundamental application approaches are different," Samsung officials explained. "The motivation for HBF is to cover a new memory semantic tiering located right next to accelerators like GPUs in server applications, whereas zNAND-O is designed to contain large-size models to interact with the NPU in on-device applications."

Targeted for 2028 in four- and eight-layer versions, zNAND-O combines high space efficiency, improved I/O performance, and low latency for edge AI environments supporting real-time, data-intensive applications.

**V10 BV-NAND: 3D NAND with Wafer Bonding**

Samsung's V10 BV-NAND represents a new iteration of 3D NAND—non-volatile flash memory with vertically stacked cells—which Samsung first introduced in 2013. Using wafer bonding technology to stack memory cells, V10 BV-NAND features more than 400 layers and increases memory density by approximately 58% over the previous V9 generation. The technology also improves read, write, and I/O performance, supporting high-performance, high-capacity storage for future AI systems.