SK Hynix and SanDisk unveil high-bandwidth flash memory technologies designed to solve AI compute bottlenecks by accelerating data movement.
At the Future of Memory and Storage (FMS) 2026 conference in Santa Clara, SK hynix and SanDisk formally released the first open technical specification for High-Bandwidth Flash (HBF) through the Open Compute Project. Developed with key ecosystem partners including Google DeepMind and Tenstorrent, this specification aims to resolve the memory wall constraining enterprise artificial intelligence infrastructure.
As parameter counts for frontier neural networks expand beyond hundreds of billions into the trillions, raw High Bandwidth Memory (HBM) capacity on accelerator packages has become a critical bottleneck. While HBM supplies the extreme multi-terabyte-per-second throughput necessary to feed modern tensor processing units, its prohibitive cost and physical interposer footprint strictly limit total capacity that can be connected to a GPU. High-Bandwidth Flash addresses this economic constraint by inserting an intermediate, high-density memory tier directly between power-dense HBM and standard PCIe-attached solid-state drives.
HBF uses high-density 3D and 4D NAND flash technology packed into dense eight-high or sixteen-high stacked die configurations, providing up to 512GB of near-compute capacity per stack. By designing this NAND array as near-memory rather than traditional block storage, AI accelerators can offload massive parameter sets exceeding HBM limits without incurring the severe latency and throughput penalties of the PCIe bus.
The paradigm is particularly suited to AI inference workloads employing Mixture of Experts (MoE) topologies or per-layer embedding offloading. In MoE architectures, only a fraction of total network parameters are active for any given token, leaving vast reservoirs of conditionally routed expert weights resident in fast memory. Because AI model serving is overwhelmingly read-heavy—with static model weights retrieved repeatedly during matrix multiplication—the write endurance constraints of NAND flash are rendered virtually irrelevant over the accelerator's operational lifespan.
To achieve near-RAM-class latencies and massive interconnect throughput, the HBF specification mandates Universal Chiplet Interconnect Express (UCIe) as its physical and protocol-level host interface. This standard, governed by a broad consortium including AMD, Intel, TSMC, and Arm, replaces the proprietary interconnects that currently limit chiplet interoperability. By utilizing UCIe chiplet packaging rather than board-level traces or PCIe lanes, HBF die stacks can sit directly on the same silicon interposer or high-density substrate as the host GPU or custom ASIC.
The initial OCP technical specification outlines three scalable bandwidth tiers—Grade 1 through Grade 3—capable of delivering host interface bandwidth ranging from approximately 400 gigabytes per second to 3 terabytes per second. When integrated with cutting-edge flash architectures like SK hynix's 375-layer V10 4D NAND, HBF promises up to 2.5 times greater power efficiency compared to standard server flash.
High-Bandwidth Flash will remain confined to enterprise data centers and custom accelerator boards. The advanced 3D heterogeneous packaging, silicon interposers, and dedicated UCIe physical layers required by HBF are economically viable only at hyperscale, making consumer adoption implausible. While enthusiast GPUs could theoretically leverage onboard NAND offloading for massive game asset caches, HBF's cost structure would make already expensive graphics cards prohibitively expensive. Instead, HBF is strictly engineered to expand LLM context windows and multi-agent AI systems in server environments.