Astera Labs releases Leo 2 CXL 3.2 memory controllers and Leo X rackscale fabric controller for disaggregated memory architectures.

Compute Express Link (CXL) enables the attachment of DRAM and other memory over a PCIe-based bus with cache coherency capabilities that allow both host-to-device and device-to-host memory access. This potential extends beyond simple capacity expansion; it opens new ways to organize and share memory across systems and larger domains.

While memory shortages have driven RDIMM prices upward, CXL offers flexibility: the attached memory need not be DDR5. All modern data center processors use DDR5, and DDR4 modules are being pulled from retired systems. Marvell's Structera line of CXL DDR4 controllers has become popular among hyperscalers seeking to mitigate DDR5 supply constraints. That concept has since spread across the industry. Now Astera Labs is advancing CXL memory expansion with its next-generation Leo controller lineup.

Over the past several years, Astera Labs has refined its Leo series of smart memory controllers. CXL-based memory expanders have allowed system vendors to exceed the capacity limits of current 16-DIMM (8-channel, 2DPC) designs. Until recently, the focus centered on total capacity. Now, as memory economics take center stage, the industry is shifting toward cost-effective ways to expand memory capacity and repurpose existing modules.

For 2026, Astera Labs believes conditions are optimal for CXL memory expansion. The company is launching Leo 2 smart memory controllers that expand DDR4 support and add CXL 3.2 and PCIe Gen6 connectivity. The latest generation also includes the Leo X, a fabric-attached controller that integrates DRAM pools directly into rack-scale system networks, dramatically expanding memory capacity within those environments.

The Leo 2 E-series and P-series represent the second generation of smart memory controllers for CPU-attached expanders. Both bring major feature updates aligned with the latest PCIe and CXL standards. Where first-generation Leo expanders used PCIe Gen5 and CXL 2.x, the Leo 2 family advances to PCIe Gen6 and CXL 3.2—the latest deployed versions that first-generation host CPUs are now launching with. This transition is significant for CXL memory standards: PCIe Gen6 doubles bandwidth per lane and per expander, effectively doubling memory bandwidth available to a system. CXL 3.x adds multi-level switching, direct peer-to-peer memory access, and support for multiple memory expanders per PCIe root port—capabilities that substantially improve the utility of CXL memory expansion.

To leverage this increased bandwidth, Astera Labs doubled the memory channels on each Leo 2 controller from 2 to 4. This doubles DDR bandwidth and total capacity per expander to as much as 768GB of DDR4 or 4TB of DDR5. The company is notably aggressive on DDR4 capacity, qualifying 4-channel, 3DPC configurations—a rare design in production systems due to complexity. This allows 12 DDR4 DIMMs per expander. DDR5 configurations are less dense, as DDR5 is difficult to run beyond 2DPC.

For data centers facing high DDR5 costs, Leo 2 expanders offer an economical path: redeploying DDR4 and older DDR5 from retired servers. Though DRAM degrades over time, and most legacy DDR4 is at least half a decade old, Leo 2 controllers emphasize RAS capabilities to make reuse viable. A hardware test engine validates each DIMM against multiple patterns, while soft-ECC runs atop the DIMMs' hardware ECC to strengthen the memory pool and catch errors beyond hardware detection. The goal is to correct faults and keep DIMMs in service rather than immediate replacement.

The Leo 2 E-series serves as the entry-level controller for single-CPU attachment. The more advanced Leo 2 P-series enables memory expanders shared between two host CPUs, permitting dynamic memory pooling instead of fixed per-CPU allocation. Astera Labs positions these controllers for AI workloads, citing use cases in large in-memory databases and local KV caches near servers—a relatively new application for CXL expanders. The argument is performance-driven: larger KV caches held in memory rather than disk enable faster token output.

Beyond CPU-attached expansion, Astera Labs' most ambitious product is the Leo X-series, a controller designed to attach memory expanders directly to the fabric networks of rack-scale AI systems. Rather than routing accelerator requests through host CPUs, memory expanders become dedicated nodes within the rack-scale network, offering accelerators direct and potentially more performant access to expanded capacity.

The Leo X-series works synergistically with Astera's Scorpio line of PCIe switch chips. When Scorpio switches compose the network fabric, Leo X-based memory expanders connect via those switches, making the memory directly accessible to all AI accelerators in the network. The highest-end Scorpio X-series switches also support CXL interfaces, enabling tighter integration between fabric switching and memory expansion.