TSMC의 CoWoS 첨단 패키징 용량은 2028년까지 연간 260,000개 웨이퍼로 두 배 증가할 예정이며, Intel과 기타 OSAT 공급업체들이 초과 수요를 확보하고 있습니다.

TSMC's advanced packaging capacity will more than double over the next two years, yet demand for AI chips continues to outpace supply, forcing customers to seek alternatives from competitors and creating unprecedented opportunities across the semiconductor supply chain.

**Capacity Expansion and Market Dynamics**

TSMC's CoWoS (Chip-on-Wafer-on-Substrate) advanced packaging capacity is expected to expand from approximately 130,000 wafers per month at the end of 2026 to roughly 260,000 wafers per month by the end of 2028. This expansion centers on Taiwan's AP7 facility and new AP9 and AP10 plants in Arizona. Despite this aggressive buildout, AI chip demand is growing faster than capacity can be added, creating a supply-demand gap currently estimated at approximately 20%—expected to narrow to around 10% by the end of 2026, but potentially widen to roughly 700,000 wafers by 2027, exceeding 30%.

The capacity shortfall is forcing major chipmakers to negotiate with TSMC more than a year in advance to secure capacity. Supply chain sources cite multiple barriers to faster expansion: high process barriers involving large-size silicon interposers, through-silicon via (TSV) drilling, and microbump bonding all require precision work and yield ramp-up time; advanced packaging equipment has lead times exceeding one year; and CoWoS capacity is tightly coupled to high-bandwidth memory (HBM) supply from SK Hynix and Samsung, making additional CoWoS capacity meaningless without corresponding HBM availability.

**Order Spillover and Competitive Alternatives**

As TSMC's capacity expansion lags demand, orders are spilling over to rival manufacturers. Analysts estimate that by the end of 2028, ASE Technology Holding and Amkor will have combined capacity equivalent to approximately 110,000 CoWoS-equivalent wafers per month. United Microelectronics and Vanguard International Semiconductor, which supply silicon interposers, are also expected to benefit from heightened demand.

Intel is entering the custom AI chip packaging market with its EMIB-T (Embedded Multi-die Interconnect Bridge) technology, which embeds a bridge within an organic substrate rather than using silicon interposers and TSVs. While EMIB-T offers lower density than CoWoS, analysts estimate it could reach 15,000 to 20,000 wafers per month by 2027 and 40,000 to 45,000 wafers per month by 2028 (when converted to 12-inch CoWoS-equivalent wafers). EMIB-T's architectural characteristics make it particularly suitable for custom AI chips from companies such as Google and Amazon. Intel's Malaysia facility has reportedly been brought in to assist with back-end advanced packaging, jointly serving major customers alongside TSMC.

**Market Structure and Capacity Plans**

TSMC Chairman C.C. Wei stated at the July earnings call that the company focuses on front-end advanced packaging and welcomes additional manufacturers to join back-end capacity to increase supply flexibility. TrendForce's Q2 2026 data shows TSMC posted revenue of $40.198 billion (approximately NT$1.3 trillion), up 12.1% quarter-over-quarter, with a 72.5% market share. The combined revenue of the world's top ten foundries reached $53.488 billion, up 11.5% quarter-over-quarter.

ASE Technology Holding's VIPack platform supports heterogeneous integration from fan-out chip packaging to co-packaged optics, with plans to invest more than $6 billion (approximately NT$190 billion) in capital expenditure to expand CoWoS-like capacity at its Kaohsiung and Central Taiwan Science Park facilities. Amkor has signed a memorandum of understanding with TSMC to provide packaging and testing support at its new Arizona facility, reducing turnaround time for wafers shipped across the Pacific.

TSMC's 5nm, 4nm, and 3nm nodes remain at full utilization, with the 2nm node contributing revenue for the first time this quarter. In advanced packaging, TSMC's SoIC (System-on-Integrated-Chip) capacity is expanding, with the 2027 monthly capacity target raised from 20,000 to 50,000 wafers, with Nvidia locking up substantial capacity. Increased demand for AI peripheral chips such as PMICs and power discrete components, along with early inventory buildup for consumer electronics, has also tightened mature-node capacity.

The advanced packaging market is shifting from TSMC's single-point dominance toward a landscape where foundries and OSAT providers expand capacity in parallel. High-end AI GPUs will continue to rely on CoWoS as the mainstream solution, while custom AI ASICs may opt for Intel's EMIB-T or solutions from other providers. The market is set to feature multiple technology routes and multiple vendors coexisting going forward.