ChangXin Memory (CXMT) releases 24-gigabit DRAM without EUV lithography, narrowing the gap with Samsung and SK hynix.

China's largest DRAM maker, ChangXin Memory Technologies (CXMT), has begun mass production on its fifth-generation manufacturing process, known as G5. The company claims the process now rivals the most advanced memory production at Samsung and SK hynix, even though CXMT has no access to the EUV lithography machines its Korean competitors use.

The headline figure is 11.95nm, the half-pitch of CXMT's memory array. Half-pitch—half the distance between repeating lines of memory cells on a chip—means a smaller number indicates greater density. CXMT says this density gain yields at least 50% more chips from each silicon wafer than its previous generation.

CXMT announced the milestone on Sunday at the 2026 World Manufacturing Convention in Hefei, alongside two LPDDR5X mobile memory chips built on G5. Both carry 24Gb per die, a 50% increase over CXMT's previous generation. They come in 496-ball and 245-ball packages for smartphones and portable electronics, and CXMT said both are already in mass production. According to Reuters, Luo Xiaodong, CXMT's vice president and head of its marketing centre, said the company's process capability is now on par with the most advanced processes in volume production.

CXMT credits the 11.95nm figure to self-aligned quadruple patterning (SAQP). This technique uses repeated deposition and etch steps to multiply the line density printed by a single lithography exposure, allowing deep ultraviolet (DUV) scanners to produce features finer than they could achieve in one pass. The choice is largely forced upon CXMT: ASML has not been permitted to ship EUV systems to Chinese customers, while Samsung and SK hynix use EUV on their leading DRAM nodes.

The company cited other process improvements. The array capacitor aspect ratio reaches 45:1, attributed to a reworked process flow and new materials. A high-k metal gate (HKMG) process adapted for DRAM cut the core area height to 6,762nm. CXMT also built a digital twin platform covering everything from design to yield maintenance to shorten development cycles. The company says G5 improves power efficiency and cost competitiveness, but has not disclosed yields that would demonstrate how well it controls the manufacturing variations that SAQP's inherent complexity can introduce.

CXMT's announcement carries important qualifications. The half-pitch, aspect ratio and core height are the company's own physical measurements, subject to standard metrology margins of error. Percentage gains are measured against CXMT's previous platform on an 8Gb-equivalent basis, according to the Seoul Economic Daily. The comparison with Samsung and SK hynix is also less direct than the announcement suggests: the Korean leaders produce on 10nm-class process technology, but 11.95nm measures one specific structure and is difficult to compare with the 12nm-class node names used by Samsung, SK hynix and Micron. Semiconductor Engineering notes that active-area pitch at 1b-class DRAM—a generation Samsung and SK hynix already produce in volume—runs roughly 22 to 26nm. CXMT's 11.95nm half-pitch equals a pitch of about 23.9nm, within that range. DRAM makers have long used generation labels rather than literal dimensions, and each defines its generations differently. The company has not disclosed G5 yields or monthly output. Until an independent teardown examines G5 chips, the 11.95nm figure rests on CXMT's data alone.

CXMT's commercial position is strengthening. TrendForce data shows the company's share of global DRAM revenue rose from 7.6% to 9.5% in the second quarter of 2026, with sales nearly doubling from the previous quarter. That ranks it fourth, behind Samsung at 39.4%, SK hynix at 24.9% and Micron at 23.3%. Reuters reported that CXMT raised RMB57.92 billion (US$8.6 billion) in its STAR Market IPO in July, Asia's largest this year, and is planning a second memory plant in Beijing. Citing sources, the report said CXMT plans a NAND flash R&D line in the capital—a move that would pit it directly against Samsung and domestic rival YMTC. Earlier this month, CXMT announced it had started mass production of LPDDR6, rated at up to 12,800Mbps, with the chip debuting in Xiaomi's 18 Fold.

Industry observers cited by Chosun Ilbo said chips from CXMT and YMTC still trail Samsung and SK hynix on performance. However, they noted that Chinese makers could gain global market share by competing on price while memory supply remains tight. Reuters reported that supply constraints have given CXMT and YMTC greater leverage with domestic customers. A Taiwanese PC maker told the Seoul Economic Daily that Chinese output has grown enough that commodity memory is no longer in short supply. The same report noted that CXMT has expanded in commodity DRAM, a segment its larger rivals have de-emphasised as they prioritise AI memory. A lower-cost supplier reaching comparable density in mobile DRAM could squeeze Samsung's and SK Hynix's margins in exactly those segments.

CXMT's HBM3E is reported to be in trial production. Its disclosures as a listed company may provide the first clear view of whether its EUV-free route to scaling holds up in volume.