Micron는 4F2 방식을 채택하지 않기로 하고, 향후 몇 년 내 3D NAND로 전환하기 전까지 웨이퍼 본딩과 High-NA EUV를 활용할 계획이다.

Having dropped 4F² memory cells from its roadmap, Micron must use different methods to keep scaling its DRAM devices in the coming years and keep pace with rivals that plan to use smaller DRAM transistors toward the end of the decade. Instead, Micron intends to introduce wafer bonding with its upcoming 1ε DRAM process technology and adopt High-NA EUV lithography for subsequent generations. Meanwhile, the company is developing new types of memory, including vertical high-bandwidth memory (vHBM) and vertical edge inference memory (vEIM), which will be integrated directly on top of processors.

"DRAM is nearing atomic limits at this point," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event this week. "Although we have confidence in several more planar nodes, we are very focused on making sure that we introduce 3D DRAM at the optimal time from a cost and performance point of view."

**Wafer bonding, High-NA EUV, and new materials**

Micron's current 1γ DRAM process is already in high-volume manufacturing. Its successor, 1δ, is scheduled to enter volume production in the second half of 2027. The 1δ node promises a mid-20% increase in bit density and is optimized for future AI memory products, including HBM5, vHBM, and vEIM. Beyond 1δ, Micron plans to introduce wafer bonding with its 1ε process, which is currently under development. However, the company has not disclosed how it intends to implement wafer bonding or what improvements it expects from the technology.

For subsequent generations, ζÅ and ηÅ, Micron plans to adopt High-NA EUV lithography and new materials, respectively, to continue shrinking DRAM cells. ζÅ (zeta angstrom) is Micron's 1st Generation sub-10nm-class DRAM node, and ηÅ (eta angstrom) is its 2nd Generation sub-10nm-class node. For many of its upcoming fabrication technologies, which will be used over the next five to 10 years, Micron is also collaborating with Albany NanoTech. As with all organizations like Albany NanoTech, the work is mostly fundamental, or pre-competitive, IP that could be used for DRAM production at some point.

"Albany NanoTech, our announced focus on advanced lithography [is] really driving High-NA EUV roadmap for DRAM," said DeBoer. "In particular at Albany with our team there, focused on the next five to ten years."

Micron is also developing 3D DRAM technologies and already lists two generations, 3D1 and 3D2, in its roadmap. However, the company has not disclosed their architectures or launch schedules. It intends to introduce 3D DRAM only when the technology offers sufficient advantages in manufacturing cost, complexity, and performance over conventional planar DRAM.

"When we look at three 3D DRAM we have that on the roadmap, as I mentioned, and it is shown here in between one zeta and one eta," said Micron's CTO. "But in reality, this is a parallel path, and we will implement it [3D DRAM] in a fashion that is ideal for cost, complexity, and device performance."

**Going vertical, becoming critical**

Beyond new process technologies for its upcoming DRAM products, Micron is working on all-new types of DRAM tailored to very specific use cases, including vHBM, vEIM, and various custom HBM (cHBM) implementations.

vHBM will place memory stacks directly on top of processors, such as AI accelerators and AI GPUs, rather than beside them. This approach promises substantially lower latency and higher bandwidth thanks to shorter connections. However, placing memory above a processor creates significant thermal challenges and limits the number of memory stacks that can be integrated on top of an ASIC. Micron therefore expects vHBM to complement conventional HBM, which will continue to provide the bulk of memory capacity in many AI accelerators.

vEIM shares architectural and packaging characteristics with vHBM but targets different applications. Whereas vHBM prioritizes maximum bandwidth for high-performance AI accelerators, vEIM focuses on energy efficiency for edge AI processors used in autonomous vehicles, robotics, and other power-constrained devices. Nonetheless, even the 1st Generation vEIM targets a formidable 2 TB/s of bandwidth at [the source text is cut off here; the remaining figure and conditions are not available].

Both vertical memory architectures will require advanced packaging technologies, particularly hybrid bonding, which enables much denser connections than conventional microbumps. Thermal management will also be critical, especially for vHBM. To meet cooling requirements, Micron is developing specialized heat-spreading structures to transfer heat from hot regions of memory base dies through the DRAM stacks.

The company has not disclosed when vHBM, vEIM, or cHBM will enter commercial production. The significance of these memory types is that future gains in memory performance will increasingly depend on advanced packaging and closer integration with processors, which will require collaboration between DRAM makers and logic developers. In turn, memory is transforming from a commodity into a critically important ingredient of ASIC design.