반도체·하드웨어 · 리포트
Next-generation AI inference chips are shifting from large SRAM to 3D-stacked DRAM, according to Technetbook.
If the pivot holds, inference silicon would depend more on stacked DRAM bandwidth than on SRAM capacity, reshaping memory supply chains and favoring vendors with HBM-class 3D packaging.
업계 전문지Slicast · 2026년 10월 21일 14:48 UTC · 미국 · 출처: Technetbook
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