AMD roadmap targets 30x improvement in accelerated datacenter GPU efficiency by 2025.

The exponential increase in data generated by people and machines requires steady growth in datacenter compute performance. To address the needs of next-generation datacenters, AMD set a goal last year to increase the efficiency of its accelerated datacenter platforms used for artificial intelligence (AI) and high-performance computing (HPC) workloads by 30 times by 2025 when compared to its 2020 platforms.

AMD recently reported on its progress toward this goal and has demonstrated considerable advancement. The energy efficiency of its accelerated platform for AI and HPC — which includes EPYC processors and Instinct compute GPUs — has improved by 6.79 times from the 2020 baseline. The company's 2020 baseline machine consisted of a server based on an EPYC 7742 CPU (64C/128T, 2.25GHz – 3.40GHz, 256MB, 225W) and four Instinct MI50 compute GPUs (5th Gen GCN, 3840 stream processors at 1450 MHz – 1725 MHz, 300W), which produced 5.26 TFLOPS per MI50 on 4k matrix DGEMM with trigonometric data initialization, and 21.6 TFLOPS of FP16 on 4k matrices while consuming 1582W.

Since 2020, AMD has released a new generation of CPUs (3rd Generation EPYC) and two new generations of compute GPUs based on its CDNA architecture, specifically designed for AI and HPC applications. AMD's 2022 reference machine is equipped with a 64-core EPYC 7003-series CPU and four Instinct MI250 compute accelerators (CDNA 2.0, 13312 SPs at 1.0GHz – 1.70GHz, 500W), which deliver 13.66 times more FP16 TFLOPS than four Instinct MI50 accelerators, accounting for much of the progress toward the 30x25 goal.

The 30x25 initiative operates as a multi-lane roadmap involving increasing raw performance of AMD accelerated datacenter hardware, improving performance-per-watt efficiency, implementing application-specific optimizations, and refining the software stack to amplify performance and lower power consumption. Future efficiency improvements will come through AMD's adoption of the DDR5-supporting 96-core 4th Generation EPYC 'Genoa' processor, which will benefit from lower power consumption of DDR5 memory compared to DDR4 SDRAM, as well as continued hardware and software refinements to CDNA performance in AI and HPC applications. "While there is more to go to reach our 30x25 goal, I am pleased by the work of our engineers and encouraged by the results so far. I invite you to check in with us as we continue to annually report on progress," said Mark Papermaster, CTO of AMD, in a statement.