Micron's G11 3D NAND is said to double bit density with over 400 layers, reaching 42 Gb/mm2 and a 5,400 MT/s interface speed for higher-capacity, faster SSDs.
Micron's next-generation 3D NAND, which will enter mass production in the second half of 2027, is set to offer three major advantages: it will double storage density, increase I/O performance by 50% compared to the company's current-generation NAND memory, and reduce power consumption, the company revealed at an event this week. To reach these aggressive targets, Micron plans to follow YMTC's lead and adopt wafer-on-wafer bonding. Micron is also developing new materials and denser memory cell architectures to extend 3D NAND scaling beyond G11.
"We had mentioned we will bring in wafer-on-wafer bonding technology at the right time when it's cost-effective, and it brings in capability that is important for the product specs at the time, and this is the right timing for that technology," said Scott DeBoer, president and chief technology and products officer at Micron, during the company's event this week. "So this G11 technology is the world's most advanced NAND. It will ramp in the second half of next year, [and] it is based on wafer-on-wafer bonding technology."
**G11: Over 400 layers and wafer bonding**
Micron's G11 3D NAND represents a substantial advance over its current G9 (N160) generation. The company expects the new memory to achieve approximately twice the bit density of G9 (3D TLC 21 Gb/mm² → 3D TLC 42 Gb/mm²?), a dramatic increase compared to Kioxia's BiCS10 or Samsung's V10. It also expects I/O speeds to increase by up to 50% (3,600 MT/s → 5,400 MT/s?) and data transfer energy consumption per bit to fall by more than 25%.
These improvements should benefit both conventional high-capacity SSDs for client and data center applications and emerging AI-oriented storage devices, which require greater bandwidth and energy efficiency.
One of the key changes introduced with G11 is wafer-on-wafer bonding, which lets Micron manufacture different parts of its NAND device on separate wafers using different process technologies: a new 3D NAND node to build the NAND array, and a logic fabrication process to make the peripheral circuits and I/O. The two are then bonded together. The company has used CMOS-under-array architectures for several generations, but wafer bonding provides additional flexibility to optimize the memory array and peripheral logic independently. If all goes as planned, this means more capacity and performance.
Another important innovation is the transition to more than 400 NAND layers. Micron has not disclosed the exact number of active wordline layers or the number of memory decks used in G11. However, the company says the technology will feature an industry-leading memory cell pitch, which suggests that its density gains will come from both additional layers and smaller cell dimensions.
Micron expects to disclose more technical details about G11 in 2027, closer to the start of high-volume manufacturing in the second half of next year.
**Beyond G11: New materials and denser memory cells**
Micron will continue scaling 3D NAND along all three dimensions rather than simply adding more layers. While conventional 3D NAND scaling initially relied primarily on adding memory layers, future generations will also require reductions in cell dimensions along the X and Y axes to improve bit density while keeping manufacturing complexity in check.
To achieve this, Micron is developing what it describes as breakthrough high-mobility materials, ultra-dense cell architectures, and more energy-efficient devices and data paths. These technologies could improve transistor characteristics, enable further reductions in memory cell dimensions, and reduce the energy required to move data within NAND devices.
"Beyond G11, we have a strong roadmap, not going to go into great detail on it today, but really focused on new materials densifying the cell architecture, and continuing to focus on that XYZ scaling going forward," said DeBoer. "[…] The current industry direction and Micron's direction is scaling both by adding layers [and] also by shrinking the cell dimensions."
The company has not disclosed specific architectural details, density targets, or production schedules for its post-G11 generations. Its roadmap nonetheless suggests that future NAND scaling will increasingly depend on innovations in materials, cell architecture, and peripheral circuitry rather than on layer-count increases alone. Still, because the number of active layers is arguably the easiest way to increase storage density, the race toward the highest layer count is unlikely to slow substantially in the coming years, especially given strong demand for 3D NAND-based storage.