AMD Instinct MI455X GPU unveiled: 320 billion transistors, 50% more HBM4 than Vera Rubin, 40 PFLOPs peak AI compute.

AMD's Instinct MI455X GPU extends the company's AI roadmap with leading HBM4 capacities and over 40 PFLOPs of compute for agentic AI, designed to rival NVIDIA's Rubin chip. The GPU will power the Helios AI rack and is based on the latest CDNA 5 architecture, fabricated using TSMC's 2nm and 3nm process technologies. The chip packs 320 billion transistors, just 16 billion shy of NVIDIA's Rubin.

AMD's Instinct MI400 series comprises three products. The MI455X and MI450X target scale AI training and inference workloads, with the MI455X powering the Helios rack. The MI430X addresses HPC and sovereign AI workloads, featuring the highest performance FP64 capabilities, hybrid compute architecture (CPU+GPU), and the same HBM4 memory as the MI455X.

The MI455X employs TSMC's advanced packaging technologies through a CoWoS-L design that integrates multiple chiplets and 3D hybrid-bonded XCDs. The high-density 3D hybrid bonds create denser die-to-die interconnects to increase compute density and performance per watt. AMD reports that CoWoS-L packaging achieves low latency and high bandwidth while enabling GPU-wide single-operation sharing techniques such as KV cache parallelism, tensor parallelism, and expert parallelism.

The eight XCDs are fabricated on TSMC's N2 process, while the IO die, fabric, and cache die use TSMC N3P. The chip contains eight XCDs with 32 work group processors (WGPs) each, totaling 256 WGPs across the chip (272 total with eight disabled). These XCDs connect to twelve 16 MB L2 cache blocks for 192 MB of shared L3 cache. The Infinity fabric connects the XCDs to twelve HBM4 controllers and 36×2 unidirectional all-to-all (UALoE) links on the Helios AI rack.

The MI455X delivers 40 PFLOPs of FP4 and 20 PFLOPs of FP8 compute—double the capability of the MI350 series. By comparison, NVIDIA's Rubin GPU offers 50 PFLOPs of FP4 and 17.5 PFLOPs of FP8 compute.

Memory capacity increases 50% from the MI350 series' 288GB HBM3e to 432GB HBM4. The HBM4 standard delivers 22.3 TB/s bandwidth—a 2.8x increase over the MI350's 8 TB/s. NVIDIA's Rubin carries 288 GB of HBM4 at 22 TB/s. The MI455X XCD features 64 KB of instruction cache per WGP, 16 KB of constant cache per WGP, 384 KB vector data and local data share, and 128 KB vector registers.

The MI455X supports NUMA and partitioning with up to eight partitions. The NPS1 profile addresses interleave across twelve HBM stacks across both dies, while the NPS2 profile interleaves across six HBM stacks without die crossing. The eight XCDs also provide up to eight spatial partitions.

AMD is introducing its MI500 (CDNA 6) accelerators in 2027, followed by MI600 (CDNA-Next) by 2028. The shift to an annual cadence mirrors NVIDIA's approach, featuring standard and "Ultra" offerings that will power next-generation AI racks and deliver substantial performance improvements.