AMD Instinct MI300 features 3D die-stacking, HBM3 memory, and PCIe 5.0 with 600W+ power draw.

AMD's next-generation Instinct MI300 accelerator will serve as the company's next-gen datacenter-focused GPU, with multiple versions expected to reach the market. According to recent leaks from Moore's Law is Dead, the architect behind the details emphasizes that "the first thing that needs to be made clear is every source tells me (Tom @ MLID) there are many variants of MI300. The one I am detailing today is just one I'm familiar with." The MI300 represents a significant step forward using CDNA 3 architecture with 5nm and 6nm process nodes, 3D die-stacking, 8 x HBM3 stack memory, PCIe 5.0 support, and power consumption of 600W or more.

The MI300's architecture centers on a complex multi-layer design. Each 6nm die features connections for two stacks of HBM3 memory and includes 12+ metal layers in total. The 6nm dies were engineered to "work with multiple products" that can be stacked on top of one another. At the foundation sits a massive interposer measuring approximately 2750mm², with a "series of rectangular 6nm tiles that house I/O controllers, IP Blocks, and likely cache" positioned on top, with each 6nm tile occupying around 320-360mm² according to the source.

The Compute Dies measure in at approximately 110mm², while the interposer reaches the substantial 2750mm² specification. Each Compute Die contains around 20,000 connections—a notably high number that represents double the connections between dies found in Apple's M1 Ultra SoC, highlighting the MI300's advanced interconnect density for high-bandwidth data transfer between components.

Power efficiency is managed through a tiered approach, with a configuration of 1 x 6nm and 1 x 5nm tile consuming 150W of power. The full high-end Instinct MI300 accelerator is expected to reach power consumption levels of 600W or so, positioning it as a high-performance solution for demanding datacenter applications.