GlobalFoundries unveiled a 7nm-class FDX Fusion process, returning to advanced FD-SOI seven years after abandoning FinFET, with production planned for 2028.
When GlobalFoundries abandoned development of leading-edge nodes in 2018, it also canceled its 7nm-class FinFET fabrication technology, which it had co-developed with IBM. Almost exactly eight years later, GlobalFoundries is back with a 7nm-class manufacturing process. This time, however, the node relies on planar transistors and fully depleted silicon-on-insulator (FD-SOI). It is aimed at automotive, edge AI, industrial, robotics, and sensor devices, as well as other products that prioritize low power consumption, high integration, and cost efficiency over maximum performance.
"We are delighted that GlobalFoundries has announced its next-generation 'single-digit FD-SOI' node, building on technology that CEA-Leti has been advancing for decades," said Sébastien Dauvé, chief executive of CEA-Leti. "Through the FAMES pilot line, CEA-Leti continues to shape the future European roadmap for FD-SOI and works every day to promote its adoption in a wide range of applications."
**FDX Fusion enters the scene**
The new fabrication technology from GlobalFoundries is called FDX Fusion. It promises 7nm-class "digital performance," an ambiguous claim that we will try to interpret later, and more than twice the transistor density of the original 22FDX process introduced around 2015. To reach its targets, the first generation of FDX Fusion will combine innovations in SOI substrates, transistor structures, and back-end interconnects. Note, however, that GF has not disclosed transistor dimensions, contacted gate pitch, minimum metal pitch, or actual transistor density. GF plans to begin production of chips on FDX Fusion at its Dresden, Germany, facility in 2028. This will mark its return to developing substantially more advanced FD-SOI processes after years of enhancing its existing 22nm-class platform.
In addition to improved "digital performance," FDX Fusion will support RF transistors with fT/fmax of up to 0.5 THz, analog and mixed-signal circuitry, embedded nonvolatile memory, and in-memory computing. The combination is intended to enable highly integrated chips that can process sensor information, execute AI inference workloads, control external devices, and communicate wirelessly without numerous separate ICs. GF also intends to provide processor IP based on MIPS, ARC, and RISC-V architectures to accelerate the development of such products.
That said, the main selling point of FDX Fusion is not necessarily its 7nm-class "digital performance" or its high-performance processor IP. It is the ability to combine relatively powerful digital logic with RF, analog and mixed-signal circuitry, embedded nonvolatile memory, and in-memory computing on a single chip. This combination, which is why GloFo calls the process FDX Fusion, could enable highly integrated SoCs that would otherwise require multiple chips made on different process technologies. That would mean additional tapeout costs as well as higher power consumption.
GlobalFoundries said it plans to deliver initial demo silicon for customer evaluation in early 2027, followed by the first process design kit (PDK) in mid-2027. The company is already collaborating with several customers on the technology, although it has not identified specific products or committed production volumes. In its press release, GF said that BMW, Bosch, Infineon, NXP, Siemens, and Tesla have expressed interest in FDX Fusion. However, only Infineon specifically confirmed collaboration on future 7nm-class technologies for radar and wireless communications.
**Significant development**
The announcement is a significant development for GF's FD-SOI roadmap. The company introduced 22FDX in 2015 and announced its 12FDX successor in 2016. That technology promised performance comparable to 10nm FinFET, full-node density improvements, and up to 50% lower power consumption. Initial 12FDX customer tape-outs were expected in 2019, but the technology was never adopted for commercial products. Instead, GF focused on enhancing 22FDX and eventually introduced 22FDX+ (around the time Samsung unveiled its 18FDS+), with additional capabilities for RF, embedded memory, and low-power applications. Interestingly, 12FDX was still part of GF's investor roadmap in 2022.
FDX Fusion could therefore represent the realization of GF's original ambition to scale FD-SOI beyond the 22nm class, although the company has not explained whether the new technology incorporates developments from its earlier 12FDX program. Meanwhile, CEA-Leti, which has researched advanced FD-SOI technologies for years, describes FDX Fusion as a single-digit FD-SOI node. Still, GF's claim of 7nm-class "digital performance" does not necessarily imply comparable transistor dimensions or integration density.
From an industry perspective, FDX Fusion could offer an alternative to advanced FinFET and perhaps even gate-all-around processes for applications that require reasonably powerful digital logic alongside RF, analog, and embedded memory. Such integration could reduce system complexity and power consumption, particularly in edge AI devices where energy efficiency and real-time responsiveness are critical. Perhaps more importantly, the technology could give European semiconductor developers access to a more advanced, locally manufactured process without depending on leading-edge foundries in Asia or the U.S.
**Questions remain**
The commercial success of FDX Fusion will depend on its actual performance, density, production costs, and the availability of a competitive design ecosystem. The last is arguably the hardest part, given the lack of comment from leading electronic design automation (EDA) and IP developers.
When GlobalFoundries claims 2X "digital performance" comparable to that of 7nm-class technologies, it doesn't specify whether it means transistor switching speed, standard cell performance, achievable operating frequency, or something else. The company also promises more than twice the logic density of its first-generation FDX technology, but it does not disclose any actual numbers. As a result, it is unclear how FDX Fusion will compare with established 7nm-class FinFET technologies. Those offer mature defect density and yields, ample supply, an established design ecosystem, and predictable pricing, among other advantages, in terms of transistor density, performance, power consumption, and production costs. CEA-Leti's comment seems promising, but actual numbers are always better.
The planned 2028 introduction of FDX Fusion will come roughly nine years after the originally anticipated first 12FDX tape-outs. That gap illustrates significant technological and/or financial difficulties in developing FD-SOI beyond the 22nm generation. So while GlobalFoundries' FDX Fusion initiative certainly looks promising, it remains to be seen how it will play out for the contract chipmaker and its clients.
For now, the lineup of supporters from the automotive and industrial sectors (BMW, Bosch, Infineon, NXP, Siemens, and Tesla) looks promising. But what about other applications? While established semiconductor companies such as Infineon and NXP already have extensive processor IP portfolios, smaller fabless developers could benefit from GF's MIPS and ARC processor cores, RISC-V expertise, and custom chip design capabilities. These could substantially reduce the cost and complexity of developing specialized SoCs. Still, to attract a broader range of chip developers, GlobalFoundries will need a mature ecosystem of EDA tools, standard-cell libraries, memory compilers, interface IP, and other silicon-proven building blocks. The press release does not address these.