Apple may return to designing and manufacturing its own server hardware for AI, signaling intensifying competition against Nvidia in enterprise and AI accelerator markets.

Apple has been reported to be evaluating a return to the commercial server market, with proposed products targeted at AI inference using its proprietary M-series chips while considering NVIDIA's NVLink Fusion interconnect technology. Apple has previously deployed custom chips for private cloud computing to support Apple Intelligence's cloud workloads. However, if the company sells servers to external customers, its products would need to operate within other enterprises' data centers and integrate with customers' networks, software, and operational systems. For a company with chip design capabilities, commercial servers still represent a business requiring external supply chain management.

The following week brought successive announcements from interconnect suppliers. On September 23, Cadence announced a demonstration of its UALink solution on TSMC's N3P process, providing silicon-verified interface designs to help chip companies adopt open interconnect standards. On the same day, network chip company Cornelis detailed its product roadmap for next-generation AI systems, planning to offload some data processing to network cards and switching chips.

Deploying custom chips in servers requires choosing which interconnect architecture to adopt and finding partners to supply interfaces, switches, and connectors. The recently disclosed interface verifications, product roadmaps, and sampling plans all center on these procurement decisions.

**Switch Market: Upgrades and Expansion in Parallel**

IDC's statistics released September 11 showed that in Q2 2026, the global data center Ethernet switch market reached $12.3 billion in revenue, growing 64.5% year-over-year. This metric covers switch equipment across hyperscale, service provider, and enterprise data centers, reflecting substantial procurement demand for data exchange between servers. Within the same report, 800GbE products' share of data center Ethernet switch revenue rose from 35.9% in Q1 to 41.2% in Q2. As the overall market expands, revenue is concentrating on higher port-speed products. As switch ports upgrade in speed, the accompanying switching chips and connectors must meet new signal transmission requirements.

Dell'Oro's September 3 report noted that in Q2, AI backend network switch sales exceeded frontend network sales for the first time. Frontend networks handle business access communications, while backend networks primarily connect accelerator servers for massive data exchange during training and inference. Purpose-built networks for compute tasks are reshaping data center network procurement structures.

Within AI backend Ethernet, 800G equipment already dominates current shipments and revenue, while 1.6T products have begun sampling, with expanded shipments expected in the second half of the year. Current procurement and next-generation validation occur simultaneously—suppliers must guarantee delivery of existing equipment while preparing new products for customers' next system designs. Whether development schedules align with customer expansion timelines directly impacts which procurement rounds a product can participate in.

Connecting accelerators and switching equipment requires cables, optical interconnect components, and high-speed signal recovery chips. Credo sells these products. On September 1, the company reported revenue of $479 million for the quarter ending August 1, up 114.7% year-over-year. These connection products have become a substantial business segment in the server supply chain.

Credo's products span copper and optical connections, covering chips, modules, and cables. The choice of computing chip does not eliminate corresponding connection requirements, but different system generations use different transmission distances, interfaces, and cabling approaches, which change the specific device combinations. Therefore, independent suppliers must follow customers' system designs to develop products, simultaneously pursuing new customers and maintaining existing system projects.

Dell'Oro predicts that the AI backend switch market will face supply constraints for at least one to two years going forward. This creates opportunities for manufacturers with delivery capacity to expand their business and makes buyers prioritize equipment arriving on schedule. Even if a cluster has secured accelerator cards, without completed network configuration it cannot operate at its planned scale—interconnect component delivery schedules must be synchronized with server procurement.

The firm also projects that current Ethernet sales in the AI backend primarily serve cross-server and cross-cluster connections, while applications for tighter accelerator interconnect will begin appearing in the second half. The product positions suppliers can pursue are extending into rack interiors, where solving faster data transmission is joined by how accelerators exchange results and coordinate execution of shared tasks.

**Custom Chips: Required Interconnect Infrastructure**

Within a server or tightly coordinated group of accelerators, chips need higher bandwidth and lower-latency connections. Both the NVLink Fusion that Apple reportedly evaluated and the UALink that Cadence verified address this requirement. They determine which interconnect architecture accelerators adopt, while interface IPs, switching chips, and connectors implement that architecture in products.

On September 10, d-Matrix announced that its next-generation Raptor chip uses NVLink Fusion combined with NVIDIA's MGX rack design, with expected shipments beginning in Q4 2027. The company focuses research on inference chips, delegating some interconnect and rack design to established platforms. For companies following this path, product development must align with the platform's interfaces, system design, and verification requirements.

UALink offers another way to organize supply chains. It is an accelerator interconnect standard that chip design companies can adopt through supporting interfaces and partner with corresponding switching chips and system vendors. Cadence's IP comprises pre-designed modules that can be integrated into customer chips; silicon verification on specified processes reduces work customers must undertake implementing the protocol specification themselves.

Interface design directly relates to manufacturing process. For companies preparing to tape out, whether standards are open is only one consideration—they must also see whether usable IP exists on their target process and whether switching chips can match system development timelines. Cadence's N3P disclosure provides concrete chip design conditions, though verification in complete customer products remains necessary.

Once an interface enters chip design, switching it later creates cascading adjustments to chips, packaging, and boards. Consequently, interconnect vendors typically compete for customers earlier than formal server procurement. Products that participate in definition and pass verification more easily enter that generation's bill of materials; other suppliers introducing comparably performing products later must seek new access to customer design and verification resources.

System vendors are also arranging products for different paths. On September 23, H3C introduced an architecture using UALink within racks and Ethernet between racks at the CloudConnect conference—first organizing multiple accelerators into tightly coordinated compute units, then linking these units into larger clusters. The company stated that the UniPoD S80000 series will support multiple mainstream interconnect protocols, preserving choices for different chip combinations.

While the same standard reduces redundant design, it does not mean accelerator cards from different vendors can already mix directly. H3C noted that multiple chips and interconnect protocols coexisting increases cross-vendor adaptation costs. Beyond interfaces, drivers, communication software, and fault handling still require joint verification. As server buyers' options increase, system vendors must maintain increasingly diverse hardware and software combinations.

For companies planning custom chips, integrating into existing platforms reuses established supply chains; adopting open standards and selecting suppliers independently preserves more combination flexibility while assuming greater integration work. Both vie for next-generation server designs, with customers comparing performance, cost, and delivery schedules of complete solutions.

**Independent Suppliers: Competing for Next-Generation Servers**

Cornelis announced $205 million in funding on September 14, with capital directed toward expanding products, manufacturing, and customer deployment. The company already provides network technology to hundreds of data centers, with CN5000 shipping and CN6000 undergoing customer sampling with expanded supply expected in Q4. Entering the intra-rack interconnect market requires continued new product development on this business foundation.

According to the roadmap further disclosed on September 23, Cornelis's next-generation CN7000 plans to support interconnect standards including UALink, providing network card and switching chip combinations. Its role is supplying hardware and software implementing interconnect; customers adopting open standards still must purchase these products to connect accelerators.

Cornelis adds value by having network equipment perform some data processing. For example, when multiple accelerators jointly train models, each calculates results requiring aggregation and redistribution; if network cards and switching chips complete partial merging as data passes through, they reduce duplicate transmission and processing on accelerators. The company also plans to support inference cache migration, reducing host communication overhead.

The company calls these features Active Compute Fabric and plans configurable processing cores enabling certain new operations to be added through firmware updates. For customers, value lies in reducing time already-purchased accelerators spend waiting for data. Specific benefits depend on tasks and system configuration; Cornelis currently publishes utilization improvements primarily from model calculations.

Under its latest timeline, the complete CN7000 implementation targets customer deployment in 2028. This generation of network cards plans to operate on standard Ethernet networks, with additional capabilities when paired with proprietary switching chips. Customers can therefore verify network cards first and, after confirming benefits, decide whether to adopt more complete product suites. Cornelis's accumulated customer relationships provide opportunities for project engagement, though the new architecture must complete its own introduction process.

Delos Data chose to address accelerator-to-network interface access. Its September 15 Data Interface release offers three forms—chiplets, near-package optical components, and boards—targeting accelerators plus CPUs, memory, and other devices. It must likewise coordinate with customers' selected interconnect protocols and system configuration, focusing on coordinating data exchange between different devices and handling certain faults at interfaces.

The three forms correspond to different collaboration stages. Chiplets require participation in next-generation accelerator design and packaging, while boards provide system-side access. Delos must therefore engage both chip design companies and customers building servers and clusters; its entry into projects depends on when customers determine chip, packaging, and network solutions.

As accelerator quantities increase, a failing chip or link can delay other devices waiting for data. Delos aims to have hardware interfaces detect faults and manage recovery, reducing impacts to overall tasks. Currently, its cluster platform operates in existing infrastructure, with new server products planned for late-2026 sampling.

In the same announcement, Delos added design and simulation tools to its cluster platform. Customers can verify real workloads using PCIe cards, test interfaces through pre-tapeout simulation, and compare different connection approaches and failure scenarios in cluster-level models. This allows chip design, network layout, and software tasks to be jointly evaluated earlier; customers can identify compatibility issues in their solutions before committing to construction.

Delos also disclosed over $100 million in funding on the same day, explicitly allocating resources to expanding software and hardware engineering teams, product development, and sales. Verification tools are also part of what it provides customers. For such companies, development investment must cover software and system support beyond interface chips, while customer implementation work continues through testing, deployment, and operations phases.

On September 21, Qualcomm, Lumentum, and Corning announced a joint demonstration plan for optical chip-to-chip connections, aiming to extend high-density connections to tens of meters via fiber optics. In this solution, Qualcomm provides chip-to-chip interface subsystems, Lumentum provides optical engines, and Corning provides optical fiber connections; electrical interfaces on the chip side and subsequent optical signal transmission require joint design. This combination targets future near-package and co-packaged optical systems but remains in proof-of-concept stage.

Buyers are also controlling combination complexity. Gimlet Labs co-founder Natalie Serrino stated in a September 21 interview that the company hopes to deploy two to four chip types per data center and find combinations that can be repeatedly deployed. Different chips can each handle their specialized computations, but increasing chip varieties also increases connection and software adaptation work.

**Conclusion**

Whether Apple returns to the commercial server market remains to be confirmed. The interconnect market is expanding, with various suppliers' products at different stages. Going forward, whether products can pass customer validation, operate stably with different chips, and meet delivery schedules will influence these companies' progress in winning orders and expanding deployments.