Nanya-backed DRAM designer Piecemakers is betting on hybrid bonding technology to fuse DRAM stacks directly to processors, aiming to bypass traditional HBM dependencies for edge AI inference.

PieceMakers, a Nanya-backed DRAM designer, began trading on Taiwan’s Emerging Stock Board on September 16 at a NT$740 reference price, Cnyes reported ahead of the debut. The company is not an HBM player. Instead, it operates on the premise that inference memory requirements diverge from those of training, President Lee Hsiao-wen told Cnyes. He added that DRAM stacked directly onto the processor via hybrid bonding can occupy a middle ground between Nvidia’s SRAM-only Groq LPU and conventional HBM. Currently, profitability stems from design fees rather than chip sales, with AI custom-design work accounting for approximately 40% of revenue in the first half of 2026. Chairman Joseph Ting told TechNews that the company’s first volume customer program will not impact financial results until 2027 at the earliest.

With roughly 60.4 million shares outstanding, the reference price valued the company at approximately NT$44.7 billion ($1.4 billion). The Emerging Stock Board serves as the Taipei Exchange’s pre-listing market rather than a main-board IPO venue, meaning shares trade through designated market makers prior to any formal listing application. The stock closed its debut session at NT$915, a 23.6% premium over the reference price, after opening at NT$1,035 and reaching an intraday high of NT$1,205. Nanya Technology remains the largest shareholder in PieceMakers, holding a 33.96% stake. It initially seeded the public float by selling 715,000 shares at NT$740, a transaction disclosed in a September 9 exchange filing reported by Knews.

Founded in January 2006 in Hsinchu, Taiwan, under the leadership of Chairman Joseph Ting and President Lee Hsiao-wen, PieceMakers historically specialized in designing standard SDR/DDR DRAM and known-good-die (KGD) components through distribution channels in China, Japan, France, Turkey, and Israel. According to a September 7 briefing reported by UDN, the company is now pivoting away from direct product sales toward custom design services billed as non-recurring engineering (NRE) fees, with plans to transition into IP licensing, royalties, and turnkey manufacturing starting in 2027. Revenue contribution from the AI custom-design segment has surged from approximately 4% in 2024 to nearly 40% in the first half of 2026. This growth is driven by two core products: HBLL (High Bandwidth, Low Latency RAM), a 2D die delivering 144 GB/s that was taped out in 2016 for Intel’s HPC line and presented at ISSCC in 2017; and HiBaLL, a 3D-stacked variant the company claims exceeds 1 TB/s. To Cnyes, the company identified its customer base as developers of cloud AI inference accelerators, international semiconductor firms, and North American clients, noting that several programs remain in design and verification phases without named accounts. While Qualcomm CEO Cristiano Amon’s Computex keynote backdrop in June featured PieceMakers among Taiwan’s ecosystem partners, neither firm has publicly clarified the nature of the partnership. Ultimately, profitability derives from design fees rather than silicon sales, aligning with the margin profile of a pre-royalty NRE business model rather than that of a traditional memory manufacturer.

Nanya’s AI memory strategy prioritizes custom, edge-focused solutions over HBM3E development. PieceMakers represents the first pillar of a strategic framework established in 2024. On August 7, 2025, Nanya announced a joint venture with Hsinchu-based chip designer Etron Technology, capitalized at NT$500 million with an 80/20 ownership split. The venture aims to develop custom high-bandwidth memory specifically for edge AI devices rather than data center accelerators. Earlier in 2025, Nanya President Pei-Ing Lee told TrendForce that the company would not enter the HBM3 or HBM3E markets. Both initiatives depend on Formosa Advanced Technologies, the testing and assembly affiliate of the Formosa Plastics Group, for advanced packaging. The facility is currently developing the through-silicon via (TSV) and die-stacking capabilities required for both ventures. Meanwhile, surging DRAM prices have solidified commodity memory as Nanya’s core revenue driver, allowing PieceMakers to function as a low-cost strategic bet that has yielded unexpected returns. Nanya recently divested approximately 3% of its PieceMakers stake, a move indicating it is operating more as a financial investor than as a parent entity actively constructing a proprietary memory stack.

Groq, an AI inference startup, entered into a $20 billion licensing and talent agreement with Nvidia on December 24, 2025. Nvidia subsequently unveiled the Groq 3 LPU (Language Processing Unit)—its first SRAM-based inference chip derived from that partnership—at GTC, its annual developer conference in San Jose, earlier this year. The Groq 3 LPU contains no HBM or DRAM. Instead, it relies on 512 MB of on-die SRAM to achieve 150 TB/s of bandwidth, significantly outpacing the 22 TB/s delivered by the 288 GB of HBM4 on each Rubin GPU. Functioning as a decode-only co-processor, it offloads prompt prefill tasks to the Rubin architecture, effectively displacing Nvidia’s previously planned Rubin CPX from its roadmap. At Hot Chips 2026, Nvidia’s Igor Arsovski—who previously served as Groq’s chief architect—confirmed that the system is in production and released the first third-party benchmark: 3,431 tokens per second on a 100K-context, 31B-parameter model. This performance sits at roughly four times the speed of the next-fastest public endpoint, though it was measured in a single-request test that we noted isn’t directly comparable to the shared endpoints it was measured against. The trade-off lies in capacity: with only 512 MB per chip, a 256-LPU rack provides 128 GB total memory, requiring 62 chips at FP8 precision merely to store the benchmark’s model weights. Nvidia has explicitly accepted this capacity limitation in exchange for decode speed, validating President Lee’s assertion that the industry leader’s latest inference hardware omits HBM entirely.

During the same Hot Chips session, Samsung’s Sangwook Han outlined a three-phase HBM roadmap culminating in zHBM, a configuration that stacks DRAM directly atop the processor rather than alongside it on an interposer. Samsung estimates zHBM will consume approximately 70% less I/O power than HBM5 while delivering roughly 2.3 times the bandwidth of a four-stack HBM4E system. Due to thermal constraints limiting stack height to approximately four layers, zHBM is projected to save around 100 W. Realizing this architecture requires wafer-on-wafer hybrid copper bonding and close co-design between DRAM and system-on-chip teams. Conversely, SK hynix VP of Package Engineering Jaesik Lee stated on August 23 that hybrid bonding will not be viable for HBM4E, making HBM5 the earliest deployment target. Industry analyst firm Counterpoint Research anticipates full-scale HBM production utilizing this bonding technique will arrive between 2029 and 2030.

PieceMakers pursues a distinct architectural approach. Rather than relying on a GPU-plus-HBM 2.5D layout, the company bonds the DRAM stack directly onto the processor using wafer-on-wafer hybrid bonding instead of traditional microbumps. This method accommodates a denser connection pitch, boosting bandwidth, while the shortened signal path simultaneously reduces latency and power draw. PieceMakers estimates its wafer-on-wafer solution delivers over 2 TB/s per layer with latency under 20 nanoseconds, targeting higher capacity than SRAM at a lower cost and power envelope than HBM. Chairman Ting emphasized that the company does not perform TSV etching or hybrid bonding in-house; these processes are managed by the customer’s logic wafer foundry. This custom integration service targets a 2027 commercialization window, contrasting with Samsung’s undated roadmap completion and SK hynix’s earliest HBM5 timeline. While Nvidia and Samsung have effectively resolved the underlying architectural debate, the critical unanswered question remains which customers will adopt the technology.

Yield remains the primary bottleneck for wafer-on-wafer mass production, President Lee noted. The repair architecture must be engineered from the outset, incorporating rigorous testing before bonding, immediately after bonding, and following final logic integration. Illustrating the compounding risk, Lee cited an 80% yield rate per layer, which drops to approximately 41% for a four-layer stack and 17% for an eight-layer configuration. This reality clarifies why PieceMakers markets repair and known-good-die (KGD) IP alongside bandwidth specifications. It also underscores the strategic fit of an IP-and-royalty business model: yield optimization IP is highly portable across diverse customers, whereas raw bandwidth metrics are not.

Looking ahead, PieceMakers’ AI-related revenue will remain predominantly NRE-driven until it secures its first named customer, with initial volume production anticipated no earlier than 2027. Chairman Ting indicated that Nanya’s third-quarter 2026 earnings report, scheduled for late October, will provide a clearer assessment of PieceMakers’ financial trajectory and disclose additional metrics. SK hynix’s hybrid-bonding timeline—which targets HBM5 at the earliest—serves as the industry benchmark, though SK hynix’s focus on 16- and 20-layer memory stacks addresses a fundamentally different challenge than integrating a few DRAM layers onto a logic wafer. Additionally, Qualcomm may soon formalize its partnership with PieceMakers. PieceMakers is positioned to evolve into an IP licensor serving a select group of accelerator developers, while leveraging Nanya and Formosa Advanced Technologies for turnkey volume manufacturing. Because the technological execution risk rests with the foundry and the end customer, the company’s upfront design-fee model remains financially sustainable. Market expectations suggest a commercial ramp spanning 2027 to 2028, slightly extending beyond Ting’s initial 2027 projection. Should the industry’s leading HBM manufacturer decline to implement hybrid bonding for its own memory products prior to HBM5, PieceMakers will be compelled to strictly adhere to its own 2027 delivery timeline.