Samsung Lee's Japan visit yielded three packaging takeaways, according to a shattered.io analysis.

Samsung Electronics Executive Chairman Lee Jae-yong spent Sunday, November 1, 2026, at the company's Advanced Package Lab in Yokohama, Japan. According to Korea Times and Korea JoongAng Daily, the visit centered on securing advanced packaging technology for AI chips and on deepening ties with Japanese materials and equipment suppliers. Korea's Financial News ran the story under a headline that quotes the goal directly: "secure advanced AI packaging technology."

### What Happened in Yokohama on Sunday

Lee toured the Advanced Package Lab, which Samsung shortens to APL, and reviewed progress on packaging materials and process technologies with the researchers working there. He also discussed how to work with Japanese suppliers, according to the Korean reports. Korea Times named two Samsung executives who accompanied him: Hiroichi Kawahira, head of the Device Solutions division's R&D unit in Japan, and Takashi Kariya, who runs the APL.

The reports describe a chairman who pressed his teams to secure advanced packaging technology and pledged to grow the lab's research staff so it can become a global R&D hub. None of the English-language coverage we reviewed carried a verbatim statement from Lee himself. The messaging came through a Samsung press release, so this article paraphrases rather than quotes.

The framing matters. Samsung's own explanation, as relayed by Korean outlets, is that lifting AI chip performance requires more than strong design and fabrication of individual chips. A company also has to link different chips together efficiently, and that linking is packaging. By visiting in person and making the point publicly, Lee signals that packaging now ranks beside logic and memory as a first-order investment.

The visit also extends a pattern. Edaily described it as part of a tour that took in Samsung's Giheung R&D complex and its Cheonan HBM production site before arriving in Yokohama. Read together, the stops trace the AI memory stack from research to manufacturing to the packaging step that ties it all into a shippable accelerator.

### The Advanced Package Lab at a Glance

The APL develops and validates the materials and processes behind advanced semiconductor packaging. Korea JoongAng Daily describes it as a facility meant to serve as a global R&D hub for technologies that improve AI chip performance. Edaily adds that it operates separately from Samsung's domestic semiconductor research institutes, while Korea Times says Samsung plans to coordinate it with the company's Korean Semiconductor R&D Center.

| Item | Reported detail | Source |

|---|---|---|

| Location | Yokohama, Japan | Korea Times, Korea JoongAng Daily |

| Established | 2023 | Korea Times |

| Official opening | September 2026 | Korea Times, Korea JoongAng Daily |

| Investment | 40 billion yen over five years from 2024 (about 350 billion won) | Edaily, Korea Times |

| Research areas | Wafer bonding, glass substrates, new packaging structures | Edaily, Korea Times |

| Visit date | Sunday, November 1, 2026 | Korea JoongAng Daily, Financial News |

| Accompanying executives | Hiroichi Kawahira, Takashi Kariya | Korea Times |

**A note on data quality.** Outlets disagree on small details, including the exact opening day and the dollar conversion of the yen budget. Where they diverge, this article keeps to the figure the majority repeats and drops the rest. The 40 billion yen budget and the five-year window are consistent across every report we checked.

### Why Japan Is the Site for Samsung's Packaging Push

Korea Times reports that Samsung chose Japan because the country already hosts an established ecosystem of materials, parts and equipment makers. Packaging lives or dies on those suppliers. Substrates, bonding tools, resins and inspection equipment decide how many good packages leave a line, and Japanese firms hold deep positions in several of those categories.

Edaily pointed to Tokyo Electron on the equipment side and Ibiden on the substrate side as examples of that Japanese supplier base. The coverage we reviewed does not say whether Lee met executives from either company during the visit, so treat those names as context rather than as confirmed meetings.

The Japanese government adds a second pull. Korea Times notes that Tokyo has designated semiconductors and AI as strategic sectors, which tends to bring subsidies, talent programs and a friendly regulatory climate. Edaily also reports that Samsung is building a second global research hub in Tokyo, scheduled for completion in the second half of 2026. Yokohama sits close enough to Tokyo to help with hiring, a point the Hankyung coverage also emphasized.

For Samsung, a lab inside the supplier cluster shortens the feedback loop. Engineers can test a new material with a partner in the same region rather than shipping samples across borders and waiting weeks for results. That speed advantage compounds when the technology under test, such as glass substrates, remains unsettled across the whole industry.

### What Advanced Packaging Does for AI Chips

An AI accelerator is no longer one chip. It is a package that holds one or more GPU dies and several stacks of high-bandwidth memory, wired together at densities no circuit board can match. Korea Times explains that advanced packaging integrates GPUs, HBM and similar components into a single package to raise performance, save space and cut cost.

Three properties follow from that integration. Bandwidth rises because memory sits millimeters from the processor. Power drops because signals travel shorter distances. Thermals become a design problem of their own, since stacked silicon traps heat. Samsung's explanation, relayed by Korean media, ties packaging directly to how quickly data moves between chips and how much power and heat the system burns.

This is why packaging shows up in model economics. A training cluster built from thousands of accelerators spends most of its energy budget moving data. If a better package cuts that movement cost, the savings multiply across every chip in the rack. Cloud buyers have noticed, and the long fight over memory supply, which we covered when Sam Altman met 50 Samsung executives, is partly a fight over who can package memory into usable accelerators at scale.

The same logic applies on the optical side. Our earlier look at Nvidia's optics-on-interposer prototype showed how substrate choices ripple into the signal path. Packaging is where chip design, materials science and manufacturing meet, and no single discipline can solve it alone.

### Wafer Bonding and Glass Substrates: The Research Agenda

The APL's stated scope is specific. Per Edaily and Korea Times, Samsung plans to extend research to wafer bonding, glass substrates and new packaging structures aimed at low-power, high-performance AI semiconductors. Each deserves a short explanation.

**Wafer bonding**

Wafer bonding joins silicon layers face to face, often without the solder bumps that earlier stacking methods relied on. Direct bonds allow far finer connection pitches, which means more signals between layers and less resistance on each one. Samsung's Q3 commentary, cov

[Source text ends mid-sentence here.]