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Intel CEO Lip-Bu Tan은 결함 밀도 지표가 목표에 근접함에 따라 14A 노드의 리스크 생산을 2027년 1분기로 앞당기고 있는 것으로 알려졌다.

차세대 가속기 도입 시 CoWoS 병목 현상 완화에 기여할 수 있는 국내 첨단 패키징 및 파브리스 용량 확보 가속화
업계 전문지Slicast · 2026년 9월 16일 19:43 UTC · 미국 · 출처: wccftech.com
중요도 80

Intel is accelerating its cutting-edge 14A process timeline, having previously shifted risk production from 2028 to the second half of 2027, and now advancing the expected commencement to the first quarter of 2027. This follows key announcements during Intel’s Q2 2026 earnings call, which highlighted the accelerated 14A risk production schedule and management’s confidence in hiking capital expenditures "significantly" next year, signaling strong visibility into confirmed orders. According to the Economic Daily, Intel CEO Lip-Bu Tan has reportedly disclosed that risk production for the 14A node will begin in Q1 2027. Meanwhile, the 18A-P node is already in risk production.

The accelerated timeline aligns with recent reports that the 14A node achieved a defect density of 0.5 in June 2026, with Intel targeting a D0 of 0.1 to 0.2 by Q1 2027. For clarity, D0 or defect density measures the average number of microscopic flaws or defects that are detected per unit area on a silicon wafer. As a particular chip fabrication process nears commercialization, its defect density typically collapses, resulting in a corresponding increase in yields. Reinforcing this progress, Intel’s David Zinsner recently noted that the 14A process is improving at the fastest pace since at least the 22nm era of 2012.

Intel’s 14A is a 1.4nm-class chip fabrication process featuring RibbonFET 2 transistors and a second-generation Gate-All-Around (GAA) architecture. This design enables tighter electrostatic control over increasingly miniature transistors, resulting in improved drive current and reduced minimum power leakage. Additionally, the node incorporates a backside power delivery system called PowerDirect, which relocates electrical wiring entirely to the rear of the silicon wafer. This frees front-side routing for data signals, thereby lowering electrical resistance and boosting transistor density.

In related developments, GF Securities analyst Jeff Pu revealed earlier this week that yields on Intel’s 18A node currently hover around 80 percent, based on figures from the Panther Lake chip lineup. Pu also projected that Intel’s 14A production could reach 6,000 wafers per month in 2027 and scale to 24,000 wafers per month by 2028.

Update: There is ongoing confusion regarding whether Lip-Bu Tan referred to Q1 2027 or Q1 2028 when discussing the 14A node’s risk production timeline. Intel has been contacted for clarification, and this report will be updated accordingly.

About the author: Writing is my one incontrovertible passion. Over the past six years, I have authored more than 2,200 distinct articles on financial and technology topics, spanning nearly one million words. I have been a member of the Wccftech mobile team since 2025. As an alumnus of the University of Toronto’s Rotman Commerce Program, I bring nuance, in-depth knowledge, and a unique perspective to every topic covered. When not writing, I travel the world exploring hidden confectionaries and restaurants as an aspiring food connoisseur. Follow Wccftech on Google to receive more news coverage directly in your feeds.

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Intel CEO Lip-Bu Tan은 결함 밀도 지표가 목표에 근접함에 따라… · Slicast