SK Hynix is shipping 16-layer HBM4 memory modules for Nvidia's Rubin GPU architecture, signaling production readiness for the next-generation accelerator.
Three companies can manufacture the advanced memory required by Nvidia's newest artificial intelligence processors. Only one has reportedly reached volume shipments with the densest configuration.
According to Silicon Analysts' latest supply-chain tracker, SK Hynix is shipping a 48-gigabyte, 16-layer HBM4 device for Nvidia's Vera Rubin platform—a step beyond the company's own previous public statements. The AI memory race between SK Hynix, Samsung Electronics, and Micron Technology has therefore moved beyond HBM4 qualification. The new competition centers on how quickly each supplier can manufacture increasingly dense memory stacks at commercial scale.
**Why 16-Layer HBM4 Matters**
HBM, or high-bandwidth memory, consists of DRAM stacked vertically next to a processor, allowing AI accelerators to receive data quickly enough to keep compute cores working. Each added layer increases capacity per stack. The 16-layer configuration holds 48 gigabytes compared to 36 gigabytes for the 12-layer version—a 33 percent increase in capacity per memory placement.
Adding four layers within the same physical footprint requires thinner dies and tighter gaps between them, making the 16-layer part the most challenging step in the generation. Silicon Analysts said SK Hynix began mass production of the 48-gigabyte, 16-layer HBM4 during the third quarter. Placing more memory directly adjacent to the processor reduces data-transfer latency and allows AI systems to run larger models without additional memory packages.
Silicon Analysts called SK Hynix's move "the sharpest supply-chain signal this week." The shipment demonstrates a capability competitors cannot replicate overnight: manufacturing yield at scale. Stacking 16 memory dies increases production complexity; each layer must communicate reliably while remaining within strict power, heat, and physical-size limits. The milestone "cements first-mover advantage" for SK Hynix.
By contrast, Micron has been in high-volume production of 12-layer HBM4 for Nvidia Rubin since March and has shipped 48-gigabyte 16-layer samples to customers, but has not announced volume production of the taller configuration. Samsung Electronics began mass-producing HBM4 in February. Its HBM3E 12-layer product cleared Nvidia qualification during the week ended September 14, and its HBM4 12-layer stack remains in the final qualification phase. Samsung told investors on its fourth-quarter 2025 earnings call that customer demand for a 16-layer product is limited and that commercializing it is unnecessary, while noting it possesses the technology to do so if requirements shift.
**Packaging Is the Binding Constraint**
Memory is no longer the slowest component in building an AI system. Silicon Analysts estimates that lead times for Taiwan Semiconductor Manufacturing's CoWoS advanced packaging have stretched to 52–78 weeks. CoWoS—Chip-on-Wafer-on-Substrate—is TSMC's advanced packaging technology for connecting Nvidia's processors with their high-bandwidth memory within a single finished AI chip package.
Without sufficient packaging capacity, additional processors and memory cannot become finished AI accelerators. As Silicon Analysts noted, "packaging, not silicon, remains the binding constraint." No merchant alternative to CoWoS exists. Capacity is expected to rise toward 120,000 to 130,000 wafers per month by the end of 2026 and 141,000 to 170,000 in 2027, but TrendForce estimates a supply gap near 20 percent this year.
Micron reports fiscal fourth-quarter results on September 30, offering the next verifiable update on HBM pricing and volumes.