d-Matrix unveiled Squadron multi-rack AI inference clusters, extending its inference hardware from single chips to full multi-rack systems.

d-Matrix announced Squadron, a fleet of multi-rack systems for AI inference at data center scale, on October 12, 2026. Founder and CEO Sid Sheth unveiled the clusters during his opening-day keynote at the OCP Global Summit in San Jose. The clusters scale to 16 SquadRacks and up to 1,024 Corsair XPUs, and systems are shipping to priority customers.

Squadron was developed in partnership with Arista, Broadcom, and Supermicro. d-Matrix has already deployed the system in its Arizona data center for internal research and development, and the clusters are shipping to priority customers for deployment in their own data centers. Squadron's building blocks, the company's Corsair servers and SquadRack rack-scale systems, are generally available. d-Matrix describes Squadron as offering megawatts of inference compute. The company said the clusters are aimed at AI labs, enterprises, and sovereign organizations running latency-sensitive applications such as coding, personal agents, cybersecurity, and high-frequency trading.

Sheth framed the launch as d-Matrix's evolution from a specialized chip company into a data center compute infrastructure business. "Customers now have access to the world's most efficient data center scale inference infrastructure available for building and ramping their ultra-low-latency AI applications," he said in the company announcement.

Supermicro president and CEO Charles Liang said the collaboration demonstrates Supermicro's ability to deliver AI technologies through its Data Center Building Block Solutions program. He said it enables customers to deploy efficient, high-performance inference infrastructure with accelerated time-to-online for advanced AI workloads and heterogeneous computing environments.

**Rack Configurations and Open-Standard Interconnect**

Squadron is available in a range of configurations that scale up to 16 SquadRacks, each a single eight-server rack, combined into one integrated cluster with up to 1,024 Corsair XPUs. The clusters are interconnected with d-Matrix's JetStream NICs and deployed with the company's Aviator software. Because the systems are air-cooled and built on industry standards, d-Matrix said customers can install them in data centers they already operate without liquid cooling or new buildouts. Customers can deploy a single Corsair server, a full SquadRack, or a multi-rack Squadron cluster on the same architecture.

The company's rack-scale product page lists four reference configurations:

- **Single-Server Starter Rack:** Eight cards with 16GB of performance memory at 1,200 TB/s, up to 2TB of capacity memory, and a power draw under 10 kW.

- **Dual-Server Starter Rack:** Two servers and 16 cards with 32GB of performance memory, rated at 10–30 kW, with Ethernet-based scale-out through JetStream.

- **Multi-Server Half-Rack:** Four servers and 32 cards with 64GB of performance memory, rated at 30–100 kW.

- **Enterprise-Ready Full Rack:** Eight servers and 64 cards with 128GB of performance memory, running models up to 100 billion parameters in performance mode.

For interconnect, d-Matrix uses PCIe to scale up within a single node and industry-standard Ethernet to scale up within a rack and scale out across racks. The company is a member of the UALink and UEC industry consortiums, which are working on next-generation scale-up and scale-out standards.

**SquadRack and Corsair Platform Background**

Squadron extends the rack-scale line d-Matrix first announced as SquadRack on October 14, 2025, at the prior OCP Global Summit, again alongside Arista, Broadcom, and Supermicro. At that event, d-Matrix described SquadRack as the industry's first rack-scale solution purpose-built for AI inference. It said the solution delivers up to three times better cost-performance, three times higher energy efficiency, and up to ten times faster token generation than traditional accelerators.

According to the 2025 announcement, an eight-node SquadRack runs generative AI models up to 100 billion parameters, with standards-based Ethernet scaling out to hundreds of nodes across multiple racks. Its listed components include Corsair inference accelerators, JetStream IO accelerators, Supermicro's X14 AI Server Platform, Broadcom PCIe switches for scaling up within a node, Arista Leaf Ethernet switches connected to JetStream NICs, and the Aviator software stack.

The Corsair platform at the center of both systems uses a chiplet-based design intended to scale SRAM beyond traditional limits. It integrates into existing PCIe-based infrastructure and supports models up to 100 billion parameters. d-Matrix's 3DIMC design stacks DRAM directly on the logic die, and the Aviator software stack is co-designed with the hardware from compiler to runtime.

**Attention-FFN Disaggregation Demonstration**

During the keynote, Sheth also disclosed that d-Matrix has implemented attention-FFN disaggregation (AFD) using a Squadron system paired with GPU servers. The company reported that offloading the model's experts and feed-forward network to Corsair racks produced 845 tokens per second per user. The heterogeneous setup reached a total throughput of 20,415 tokens per second with 64 concurrent users. d-Matrix said it is the first to show AFD running on real, currently available silicon.

A companion technical post published October 12, 2026, describes the test setup. The workload is GPT-OSS-20B, a mixture-of-experts model in which the experts account for 19.12 billion of 20.9 billion total parameters. Four of 32 experts are active per inference, roughly 3.6 billion parameters. At four-bit precision, those experts fit on an eight-card Corsair server with 16GB of SRAM. An 80GB Nvidia H100 GPU handles attention, embeddings, KV cache, and expert routing, while Corsair runs expert computation. At a batch size of 64, two H100 GPUs share eight Corsair accelerators.

d-Matrix said Corsair's SRAM provides 150 TB/s of memory bandwidth, which it describes as 45 times the HBM3 bandwidth on an H100 and roughly nine times the 18 TB/s offered by HBM4. The company reported that moving the feed-forward work to Corsair cut time per output token from 2.59 milliseconds on a lone H100 at a 1K context length to 1.28 milliseconds, a reduction of roughly 50 percent.

The post describes 24 round trips between the GPU and Corsair for the model's 24 layers, plus one more for the LM head. The GPU sends a 2,880-dimension hidden-state vector and target expert assignments across JetStream links that provide 400 Gb/s of Ethernet bandwidth per cluster. JetStream's device-initiated communication lets the GPU write directly into Corsair memory and lets Corsair write results back without host CPU involvement. Each Corsair card holds one shard of the LM head, an arrangement d-Matrix said cut the LM head's processing time by a factor of ten.

At a batch size of 64, the company said the system completes a full 64-user decode step in 2.46 milliseconds at a context length of 129. d-Matrix also said Corsair can scale speculative-decoding and AFD configurations to models in the hundreds of billions of parameters, naming GLM 5.x and Kimi K3 as targets.

d-Matrix researchers will present the AFD demonstration live at the company's OCP booth C82 on October 14, 2026, at 11 a.m. and 2 p.m. PT, and on October 15, 2026, at 11 a.m. PT.