Samsung presented a more polished generation of its LPDDR5X-PIM processing-in-memory solution at Hot Chips 2026.

Samsung presented LPDDR5X-PIM at Hot Chips 2026, unveiling a processing-in-memory solution built on LPDDR5X DRAM specifically optimized for AI inference. The session was highly anticipated by industry observers attending the event.

Samsung opened its presentation with market data framing memory costs as a growing percentage of AI package expenditures. High-bandwidth memory (HBM) now accounts for the majority of AI chip component spending, rising from 52 percent in Q1 2024 to 63 percent by Q4 2025, with current figures likely even higher. While HBM delivers the bandwidth required for AI inference, it carries high power consumption and complex packaging requirements. Samsung argues that reducing costs requires shifting to a new memory form factor: low-power processing-in-memory (LP-PIM).

The company outlined its PIM development timeline, tracing progress from the Aquabolt-XL HBM2-PIM proof of concept in 2021 to the 2026 productization of LPDDR5X-PIM, which Samsung claims is the world’s first LPDDR-based PIM solution. For background on earlier iterations, readers can refer to coverage of Samsung’s HBM2-PIM and Aquabolt-XL at Hot Chips 33, as well as its Processing in Memory Technology presentation at Hot Chips 2023.

Architecturally, LPDDR5X-PIM integrates sixteen PIM blocks within the DRAM banks. These blocks feature parallel MAC trees and an arithmetic logic unit (ALU) capable of handling both floating-point and integer calculations. The specification utilizes a JEDEC-standard 561-ball package containing 16 GB distributed across four dies per rank, targeting server, mobile, and client applications. At an x64 configuration operating at 9600 Mbps, PIM bandwidth reaches 614 GB/s—eight times the 76.8 GB/s available through conventional DRAM interfaces.

LPDDR5X-PIM marks the first LP-PIM product to support multi-precision data types. Users can select from fifteen combinations via MAC precision fields in the configuration register. Depending on the workload, activations paired with SINT4 weights deliver 2.4 TOPS, while FP8 configurations yield approximately 1.2 TFLOPs per package. Drop-in compatibility is maintained through Address Align Mode, which maps DRAM addresses to MAC instructions, allowing the chip to operate with existing DRAM controllers rather than requiring custom hardware.

The architecture supports dynamic switching between single-bank and multi-bank PIM operations using predefined rows and dedicated PIM registers. Samsung notes this method offers faster and more reliable transitions than the HBM-PIM approach used in previous generations. The MAC execution flow begins with an activation write phase, where sixteen WRPB commands populate source register files across the banks with FP8 activation data broadcast from the host processor. Next, the weight matrix loads via PIMX_RD, which reads 32-byte weight elements directly from DRAM cells, distributes them across the MAC trees, and aggregates the results into a single vector register file. As each MAC operation completes, partial sums are stored in the vector register file before PIMX_WR transfers the data back to the DRAM bank. This design decouples the read-to-write ratio from a fixed 1:1 constraint. To retrieve final results, the host switches to single-bank mode and issues sequential RD commands, with up to 64 reads sufficient to service the 1-kbit vector register file.

Samsung validated the design on silicon using its edge AI accelerator SoC, testing both standard LPDDR5X and LPDDR5X-PIM configurations. The benchmark ran Llama-3.1-8B with a 320-token context window, utilizing SINT8 activations, SINT4 weights, and SINT32 outputs. Under these conditions, the LPDDR5X-PIM implementation completed the task in 5.4 seconds compared to 12.3 seconds on conventional LPDDR5X, representing a 2.28x speedup. Inference throughput increased from 27.0 tokens per second to 81.3 tokens per second, a 3.01x improvement that underscores the technology’s value proposition.

Samsung emphasized that software and ecosystem support are integral to the platform. A simulator and datasheet are available upon request, and the accompanying SDK includes reference tooling. Looking ahead, LPDDR6-PIM is progressing toward a finalized JEDEC LP6-PIM specification. Achieving JEDEC standardization represents a critical milestone in transitioning PIM from research prototypes to commercially viable products.

Strategically, Samsung is positioning LPDDR5X-PIM as a cost-effective, lower-power alternative to HBM for AI inference workloads, with silicon validation demonstrating tangible performance gains. However, widespread adoption will likely require anchor customers to champion the technology, integrate it into their designs, and drive industry momentum. The shift also introduces a strategic consideration: when memory vendors assume control over both storage and compute layers, they gain significant leverage in customer relationships. Consequently, robust standardization remains essential to enable second-sourcing and prevent vendor lock-in.