AMD showcased its Versal RF Series devices at Hot Chips 2026, featuring hardened IP blocks integrated with flexible FPGA fabric.
AMD is presenting its Versal RF Series at Hot Chips 2026. This adaptive system-on-chip family targets wideband radio frequency signal processing across defense, test and measurement, communications, and quantum control applications.
AMD’s integrated RF development timeline spans from the Gen 1 RFSoC parts introduced in 2018 through the 2023 DFE family, with RF bandwidth increasing from 4 GHz to 7 GHz. The Versal RF Series marks a significant architectural leap from the earlier Zynq platforms toward the 2025 Versal generation. AMD claims the new devices deliver up to 19 times the digital signal processing compute and 6.4 times the maximum sample rate compared to previous generations. The latest parts achieve 32 gigasamples per second on the analog-to-digital converter side and support 18 GHz of RF bandwidth, a substantial increase over the 5 GSPS and 6 GHz offered by Gen 3. The family delivers up to approximately 80 tera-operations per second of effective DSP compute.
Processing wideband signals requires managing massive data volumes while adhering to strict size, weight, and power constraints at the far edge. The signal chain routes data from the RF-ADC through a first-stage channelizer into the AI Engine array, followed by a second-stage channelizer and general-purpose compute. This architecture compresses an 18 GHz input signal down to approximately 1 MHz for efficient analysis.
The architecture integrates hardened intellectual property, a dedicated processing system, and the AI Engine array. Control tasks are managed by two Arm Cortex-A72 cores and a pair of Cortex-R5F processors, while bandwidth-intensive DSP functions are offloaded to hardened blocks including FFT/iFFT, channelizers, LDPC decoders, and poly-phase filters. The device supports RF-ADCs up to 32 GSPS and RF-DACs up to 16 GSPS across 18 GHz of RF bandwidth, complemented by DDR5 and LPDDR5X memory alongside Universal Chiplet Interconnect Express chip-to-chip links.
Continuing the Versal platform’s evolution from High Bandwidth Memory to LPDDR5X Memory-on-Package, AMD has significantly increased on-chip memory capacity. Hardened IP serves as the primary mechanism for converting raw bandwidth into manageable compute loads. The hardened FFT/iFFT blocks operate at up to 4 GSPS with transform sizes ranging from 8 to 4096 points, while the channelizer divides wideband inputs into multiple narrow sub-channels at speeds up to 8 GSPS. Implementing these functions in silicon rather than soft programmable logic substantially boosts DSP throughput while reducing power consumption.
The Versal RF Series launches with four initial devices alongside a UCIe-capable variant. The VR1602 and VR1652 models focus on wideband capabilities; the VR1602 features sixteen 8 GSPS ADCs, while the VR1652 utilizes four 32 GSPS ADCs to achieve the highest sampling density on a single die. The VR1902 and VR1952 variants expand DSP engine counts and include a poly-phase block for enhanced flexibility. All devices in the family utilize 14-bit data converters.
Wideband performance originates in the converter tiles. An RF-ADC quad tile provides four channels at 8 GSPS each at 14-bit resolution, while an RF-DAC quad tile delivers four channels at 16 GSPS. A standalone ADC tile supports up to 32 GSPS. All tiles maintain DC-to-18 GHz bandwidth. AMD reports aggregate data rates of up to 256 GSPS—equivalent to 4 terabits per second—flowing from the ADCs directly into the on-chip DSP fabric.
AMD categorizes computational workloads by function and device tier across the VR16xx and VR19xx families. In peak channelization scenarios, total DSP throughput reaches approximately 31,104 giga-operations per second. Because a significant portion of computation is handled by hardened IP rather than the programmable fabric, these Versal devices increasingly transcend traditional FPGA classifications.
Each hardened FFT/iFFT block sustains 4 GSPS in streaming mode. The VR16xx series incorporates 28 such blocks, while the VR19xx series includes 36. They support power-of-two transform sizes from 8 to 4096 points, with dynamic reconfiguration of both point size and FFT direction. AMD estimates that using hardened blocks reduces power consumption by approximately 87 percent compared to equivalent soft-logic implementations.
The second-stage channelizer functions as a downstream filter bank. Each block operates a 64-tap prototype filter at a native 1 GSPS rate and can be configured as an eight-channel polyphase filter utilizing either complex or real taps. The VR16xx devices integrate 224 of these channelizer blocks, while the VR19xx series scales up to 480 instances, each consuming merely 0.035 watts.
The hardened Low-Density Parity-Check decoder IP is optimized for 5G and satellite communication links. The block sustains throughput rates of 7.7 Gb/s for 5G New Radio at eight decoding iterations, 4 Gb/s for DVB-S2, and 3.7 Gb/s for DVB-S2X. Notably, 5G NR decoding requires zero programmable logic resources. AMD states that integrating four of these decoders delivers computational capability comparable to an entire Virtex UltraScale+ VU13P FPGA.
The poly-phase block is exclusive to the VR19xx devices. A single hardened unit consolidates eight distinct functions, ranging from single- and multi-channel finite impulse response filters to arbitrary resamplers and matrix multipliers, accessible via five configurable soft IP layers. This design provides a highly adaptable foundation for advanced resampling and channelization architectures.
The AI Engine array serves as the primary programmable engine for wideband DSP tasks. Featuring up to 126 tiles, each equipped with a very-long-instruction-word processor operating above 1 GHz alongside integrated memory, the array efficiently manages high-throughput signal processing. AMD reports that the AI Engine array consumes approximately 20 percent less power than equivalent implementations using solely programmable logic.
Benchmarking a 32,000-point FFT at 8 GSPS demonstrates significant efficiency gains: deploying the AI Engines alongside programmable logic reduces lookup table utilization from over 153,000 to approximately 8,000, decreases latency from 48 microseconds to 7.5 microseconds, and lowers dynamic power consumption by up to 30 percent compared to a pure programmable-logic architecture.
The architecture strategically balances four distinct compute paradigms, each optimizing the trade-off between efficiency and flexibility. Hardened IP and dedicated DSP engines manage the highest sample rates and standardized signal processing functions. The AI Engine array executes broad-spectrum wideband processing, while the programmable fabric integrates these components into customized system architectures. AMD positions this hybrid approach as deploying hardened IP where computational efficiency is paramount, and programmable fabric where architectural flexibility is required.
Size, weight, and power optimization remains a critical advantage for far-edge deployments. AMD states that a single VR1602 or VR1652 delivers DSP compute equivalent to four Virtex UltraScale+ VU13P FPGAs, combined with the programmable logic and AI Engine resources of a Versal AI Core VC1702, all within a compact 37.5 × 37.5 mm package. Consolidating this level of silicon integration into a single adaptive SoC addresses the stringent form-factor requirements of space-constrained platforms.
Quantum control represents a distinctive target application highlighted during the Hot Chips 2026 sessions. AMD is addressing the latency hierarchy inherent in quantum computing systems, bridging millisecond-timescale operations like error decoding and correction with nanosecond-timescale tasks such as pulse generation and qubit readout. Within this architecture, the Versal RF series operates between the host CPU/GPU compute stack and the quantum processing unit.
The Quantum Instrumentation Control Kit builds upon AMD’s RFSoC heritage. Developed in collaboration with Fermi National Accelerator Laboratory, Oak Ridge National Laboratory, and the U.S. Department of Energy, QICK leverages a unified single-chip CPU, FPGA, and radio platform for open-source qubit control and readout. The Versal RF series enhances this framework by providing higher bandwidth for expanded read-channel multiplexing, simplified frequency planning, and offload capabilities via high-speed Ethernet or PCIe Gen5 interfaces.
Demonstration configurations for the VR1952 illustrate multiple independent wideband receive paths operating from a single device. Each antenna feed covers a 4 GHz segment, allowing a small array of feeds to span approximately 2 to 18 GHz. Deep channelization reduces individual sub-channel data rates to roughly 31.25 megasamples per second, granting operators continuous, wideband spectrum visibility instead of relying on narrow-tuned reception windows.
Universal Chiplet Interconnect Express support establishes a clear expansion pathway for the Versal RF family. The devices feature UCIe-SP x16 interfaces operating at up to 16 gigatransfers per second, alongside UCIe-AP x64 or x32 links. This architecture enables designers to integrate up to four additional chiplets via a silicon interposer. AMD anticipates ecosystem adoption of commercial and custom chiplets targeting RF front-end processing, artificial intelligence acceleration, and specialized compute workloads.
This architecture stands as a tangible realization of the strategic vision originally articulated by Victor during Xilinx’s launch of the Versal family. Under AMD, those foundational concepts have matured into a cohesive platform that seamlessly blends hardened intellectual property with highly flexible programmable fabric, demonstrating a clear evolution in adaptive computing design.