SK hynix presented challenges around HBM packaging for AI accelerators at Hot Chips 2026.
SK hynix’s Hot Chips 2026 presentation centered on high-bandwidth memory (HBM) and advanced packaging, detailing the 3D stacking, bonding, and system integration strategies underpinning next-generation HBM architectures. SK hynix defined HBM as a three-dimensional stacked structure comprising a base die and up to 16 core dies. In a 2.5D package, the GPU and HBM share a silicon interposer, communicating through 1,024 I/Os across 16 channels—organized as four slices per rank and four ranks within a 16-die stack. The interposer interface remains critical, as it represents the primary junction between HBM and the accelerator. Advancing HBM technology is driven by the need for higher bandwidth, greater capacity, and improved power efficiency.
Although HBM carries a higher per-gigabyte cost, SK hynix emphasized that broader adoption reduces overall system footprint, power consumption, and operational expenses. The company illustrated this by comparing configurations of twelve GDDR6 sites against four HBM3E sites, demonstrating superior space efficiency alongside increased bandwidth and capacity. While direct architectural comparisons can vary depending on specific implementations—such as the 32 GB of GDDR7 memory in consumer-grade GPUs like the NVIDIA GeForce RTX 5090—the systemic advantages of HBM remain evident.
Each successive HBM generation delivers substantial gains in capacity and bandwidth. HBM2E achieved 460 GB/s, HBM3 scaled to 717 GB/s, and HBM3E reached 1,024 GB/s. HBM4 doubles peak throughput to 2,048 GB/s across 2,048 I/Os. Physical dimensions also expand, with the package footprint growing from a 10×11 mm base to 12.4×11 mm for HBM4. HBM4 incorporates a significantly higher density of through-silicon vias (TSVs) and micro-bumps. SK hynix specified over 20,000 TSVs and 16,148 base micro-bumps on a 12.8×11 mm component with a 775 μm Z-height. The design targets over 2 TB/s of bandwidth, delivering a 40% or greater improvement in power efficiency alongside enhanced thermal resistance. Total capacity reaches 48 GB, with 12-die stacks currently in production and 16-die stacks undergoing qualification.
Die-to-die stacking relies primarily on two bonding methodologies, each presenting distinct trade-offs. Thermo-compression bonding with non-conductive film (TC+NCF) enables high productivity and low thermal resistivity but remains highly sensitive to chip warpage. Conversely, mass reflow with molded underfill (MR+MUF) accommodates thin-die warpage more effectively, though it introduces higher thermal resistivity and a narrower gap-fill tolerance. The selection between these approaches directly influences downstream manufacturing yield and thermal performance. SK hynix executes a comprehensive wafer-level fabrication flow for HBM assembly, encompassing silicon etching, TSV copper filling, back-end-of-line (BEOL) metallization, wafer thinning, back-side processing, singulation, and testing. A known-good stacked die (KGSD) verification step enables pre-packaging testing of individual die stacks, ensuring that defective units do not consume valuable interposer area during system-level integration.
The most significant packaging challenges reside in TSV formation, micro-bumping, wafer thinning, and die stacking. SK hynix identified process uniformity, yield consistency, and copper contamination as primary concerns during TSV and bump fabrication. Additional complexities include thin-die handling and warpage management throughout wafer thinning and underfill-based stack assembly. The introduction of a 16-die HBM3E configuration delivering 48 GB per stack represents a major packaging milestone. Expanding beyond the previous 12-die limit required maintaining the same Z-height budget, necessitating approximately 50% reductions in die thickness, inter-die gap height, and bump pitch. These dimensional adjustments were achieved without compromising underfill gap-fill integrity.
As stack heights approach 20 or more dies, thermal management emerges as the primary limiting factor. Thermal resistance decreases progressively across bonding and material-stack architectures, transitioning from standard molded underfill to advanced MR-MUF and ultimately hybrid bonding. Each architectural advancement supports additional die layers while improving heat dissipation. Hybrid bonding fundamentally alters stack assembly methodology. Components are aligned and placed at room temperature, followed by an annealing process exceeding 200°C that creates direct SiO₂-to-SiO₂ and Cu-to-Cu bonds. This mechanism eliminates the reliance on traditional micro-bumps and gap-fill materials used in prior generations. SK hynix identifies hybrid bonding as the enabling technology for 20-die and taller stacks, offering expanded performance capabilities through tighter pitch geometries and enhanced thermal conductivity. Within a fixed Z-height envelope, hybrid bonding permits the use of thicker die cores while achieving pitches below 18 μm—a specification unattainable with MR-MUF processes.
SK hynix benchmarked its thermal strategy against competing industry approaches. Its i-HBM architecture integrates a high-thermal-conductivity, electrically insulating cooling element directly into the active die-to-die PHY region, establishing a dedicated thermal pathway designed to reduce thermal resistance by more than 30%. Competing solutions include Samsung’s High Performance Base (HPB), which relocates DRAM adjacent to the processor using a copper heat spreader, and Micron’s optimization of base-die circuitry for improved power efficiency.
Looking beyond HBM4, SK hynix outlined two primary development vectors. The first increases bandwidth by expanding data I/O counts and elevating per-I/O transmission speeds. The second enhances power efficiency through a dedicated logic base die and increased TSV density. Bandwidth scaling is driven by higher data I/O volumes and accelerated signaling rates, supported by integrated logic processes. Per-device bandwidth scales from 0.5 TB/s in HBM2E to 2.0 TB/s in HBM4. The transition from HBM3E to HBM4 doubles I/O speed while pushing the data I/O count beyond 1,000. Power efficiency improvements rely on an optimized logic foundry process and strategically distributed power TSVs that enhance the power delivery network (PDN). SK hynix reported a 75% improvement in PDN performance across recent HBM generations, sustained by continuous scaling of low-power logic architectures.
At the system level, SK hynix highlighted a fundamental shift in assembly sequencing. Historically, memory modules were integrated late in the manufacturing flow. In modern AI advanced packaging, HBM is assembled first, subjecting both the die stacks and the silicon interposer to heightened reliability demands before subsequent package layers are added. The company evaluated major advanced packaging architectures—including TSMC’s CoWoS-S, CoWoS-L, and Intel’s EMIB—to assess their respective mechanical and thermal loading profiles on HBM stacks and interposers. The selected packaging methodology directly dictates the magnitude of stress the HBM assembly must endure during operation. SK hynix categorized packaging evolution into three hierarchical tiers: die-to-die stacking, die-to-interposer integration, and package-to-board assembly. Positioning HBM within this framework underscores its placement in the most technically demanding tier, explaining the industry’s intense focus on advanced stacking and bonding techniques.
Compared to other presentations at Hot Chips 2026, SK hynix placed exceptional emphasis on packaging engineering. The session demonstrated that HBM development has evolved into a tightly coupled co-design challenge, where bonding methodologies, thermal management, and interposer stress factors are deeply interconnected. While the presentation did not extensively cover custom HBM configurations or next-generation HBM5 specifications, the detailed roadmap establishes a clear foundation for future advancements. Further technical disclosures on these topics are anticipated in upcoming industry briefings.