SK Hynix detailed its adoption of Intel EMIB and other advanced packaging technologies for next-generation HBM memory while targeting future 3D structures.

SK Hynix is leveraging advanced packaging technologies, including Intel’s EMIB, for its next-generation HBM solutions, with a clear trajectory toward 3D packaging. At Hot Chips 2026, Jaesik Lee of SK Hynix delivered a presentation titled “Advanced Packaging for High-Bandwidth Memory,” outlining how the company intends to utilize advanced packaging techniques to accelerate its HBM roadmap.

The presentation began with an overview of current HBM construction. HBM utilizes a 3D stacked architecture that connects multiple core dies (DRAM ICs) to a base die via Through-Silicon Vias (TSVs). Presently, HBM supports a maximum height of 16 slices, or a 16-Hi stack. Each rank comprises four slices, meaning a 16-Hi stack contains four ranks. Each slice features four channels, incorporating a total of 16 banks. While HBM and GPUs remain separate chips, they are mounted on a shared silicon interposer using 2.5D packaging. Each HBM module includes 1,024 I/O pins with 16 channels routed through the silicon interposer, connecting the HBM stack to the XPU via a PHY.

HBM serves as a critical DRAM alternative by reducing space, power consumption, and operational costs. A typical GDDR6 configuration delivers 24 GB of memory with 768 GB/s of bandwidth, whereas an HBM3E solution with four stacks occupies roughly half the space while providing up to 144 GB of capacity and 4 TB/s of bandwidth. SK Hynix’s current roadmap positions HBM4 as its flagship product, featuring up to 24 Gb DRAM densities, capacities reaching 36 GB, 2,048 I/O bits, I/O speeds up to 8 Gbps, and bandwidth up to 2,048 GB/s.

HBM4 introduces increased package height and footprint compared to previous generations, integrating more TSVs and micro bumps than HBM3E. The industry currently relies on two primary packaging methods: Thermo-Compression + Non-Conductive Film (TC+NCF) and Mass Reflow + Molded Underfill (MR+MUF). TC+NCF provides superior resistance to die warpage but suffers from higher thermal resistivity and lower manufacturing productivity. Conversely, MR+MUF delivers higher productivity and lower thermal resistivity but is more prone to chip warpage and exhibits gap-fill limitations. SK Hynix outlined its HBM process flow, spanning six key stages from fabrication to customer systems, and highlighted four core technologies integrated within its HBM packages. Among these, Advanced MR-MUF is already deployed in SK Hynix’s 16-Hi HBM3E solution, incorporating Warpage Control and Fine Pitch Interconnect & Narrow Gap-fill enhancements. These refinements increase the total package height to 775 microns while reducing chip thickness to 0.9x, gap height to 0.5x, and bump pitch to 0.9x.

Looking ahead, SK Hynix identifies two primary challenges: escalating HBM power demands as bandwidth requirements grow, and thermal management compounded by TSV area constraints. As TSV counts rise, the occupied area expands even as TSV pitch dimensions shrink. Additionally, bandwidth nearly doubling every two generations imposes a 2.2x thermal burden on existing processes and packaging technologies. To surpass 16-Hi stacks, SK Hynix is exploring hybrid bonding, which enables narrower pitches for higher performance and improved thermal conductivity for better efficiency. Data indicates that hybrid bonding supports a 24% thicker core die and achieves a TSV pitch of less than 18 microns compared to MR-MUF processes. Despite accommodating more stack layers, hybrid bonding reduces thermal resistance by 35%.

Mirroring Samsung’s HPB (Heat Path Block), SK Hynix is developing a proprietary localized hotspot mitigation technology called I-HBM. This approach embeds a high-thermal-conductivity, electrically insulating cooling component directly into the HBM D2D PHY region near hotspots, establishing a dedicated heat path that cuts thermal resistance by an additional 30% or more. In the long term, SK Hynix aims to double TSV counts and increase I/O speeds through logic process integration. Power delivery network (PDN) challenges will be mitigated using optimized logic foundry processes, with power TSVs distributed extensively to significantly enhance PDN performance.

The continuous drive for higher power density, bandwidth, and stack heights in HBM technology introduces substantial thermal, mechanical, and packaging hurdles, exacerbated by thicker oxide layers, denser TSV arrays, and faster pin speeds. Innovations such as MLMO, optimized micro-bumps, emerging hybrid bonding (delivering improved thermal conductivity, broader process margins, and finer pitches), and hotspot management solutions like I-HBM are actively resolving these constraints. As stacks advance toward 16–20 Hi configurations and architectures shift toward tighter 3D integration with logic, success will require rigorous co-optimization of design, materials, customer processes, and interposer technologies. Sustained cross-industry collaboration remains vital to satisfy future workload demands for both capacity and bandwidth. During the presentation, SK Hynix also highlighted Intel’s EMIB packaging technology alongside TSMC’s CoWoS-L, CoWoS-R, and CoWoS-S in its 2.5D HBM solution architecture, illustrating how each advanced packaging method applies distinct mechanical and thermal stresses to the HBM and interposer. Ultimately, SK Hynix is positioning itself for 3D integration, which would enable stacking HBM directly atop accelerators—a strategic objective the industry awaits until advanced logic and packaging technologies fully mature.