At Hot Chips 2026, SK hynix details how its hybrid bonding HBM5 architecture overcomes the 775-micron thickness limit by extending MR-MUF packaging through the Nvidia Rubin generation.

At Hot Chips 2026 on August 23, Jaesik Lee, vice president of package engineering at SK hynix America, outlined the physical constraints capping HBM stack height and confirmed that hybrid bonding will miss HBM4E, pushing the packaging transition to HBM5 at the earliest. The fundamental limit stems from the standard 300mm logic wafer thickness of 775 microns, which caps total HBM cube thickness. As Lee explained, any additional DRAM layer must therefore rely on thinner dies and narrower inter-layer gaps.

The JEDEC HBM4 standard increased the package thickness ceiling from 720 microns—maintained through HBM3E—to 775 microns, alleviating some pressure ahead of hybrid bonding adoption. When a GPU cold plate is attached, both the logic die and memory stacks are ground back to expose bare silicon. Because logic wafers are fixed at 775 microns, a taller memory cube would protrude beyond the adjacent processor. “That’s the kind of limit that we can go up so far, because the logic wafer thickness is also 775 microns,” Lee said. Thinner dies inherently increase the proportion of poorly heat-conductive oxide in the stack, while pin speeds have surged from 1 Gbps in early HBM to 8 Gbps in HBM4, concentrating more power in the same footprint. SK hynix data indicates the thermal burden has risen 2.2 times across the generations presented, even as stack counts double every two generations.

Currently, 12-Hi HBM is in mass production, while 16-Hi HBM4 is undergoing customer qualification at 48GB per cube. To achieve this, core dies are thinned to approximately 50 microns, and inter-layer gaps are halved compared to 12-Hi. SK hynix’s mass reflow-molded underfill (MR-MUF) process, which pick-and-places all dies and bonds them in a single reflow step, already operates near its margin limits. Filling gaps that have shrunk by half while controlling warpage on sub-50-micron dies represents the primary manufacturing challenge for 16-Hi, according to Lee.

While Samsung publicly committed to hybrid bonding for HBM4 last May, SK hynix has treated the copper-to-copper technique as a backup behind advanced MR-MUF. The recent JEDEC thickness relaxation removed the immediate necessity, and industry discussions are now weighing a further increase to 825–900 microns for 20-Hi stacks, which would delay the crossover to copper bonding even longer. In March, industry sources reported that SK hynix placed its first mass-production hybrid bonding order: a single inline system combining Applied Materials and Besi tools valued at roughly 20 billion won ($15 million). Counterpoint Research projects the technique will enter full-scale HBM production alongside HBM5 around 2029 to 2030.

According to SK hynix’s roadmap, hybrid bonding remains in the research phase for 20-layer and above stacks, and the company has yet to designate which product will receive it first. Ruling out HBM4E leaves HBM5 as the earliest viable slot. The process bonds flattened copper pads and oxide surfaces at room temperature, then leverages copper’s thermal expansion during a curing step to form the connection. “This is a very simple process, but in reality it’s really challenging,” Lee said. “We are talking about 16 layers and 20 layers that we need to make the hybrid bonding, so it’s very different from the one-layer stacking.” Eliminating micro-bumps allows core dies to grow up to 24% thicker at 20-Hi, reduces thermal resistance by approximately 35% compared to MR-MUF at that height, and pushes bump pitch below 18 microns, down from the 30 microns currently used by MR-MUF. At HBM4’s existing bump pitch, conventional micro-bumps remain functional, and historically, each JEDEC thickness relaxation has kept MR-MUF viable for another generation.

Three months after its May unveiling, Lee detailed SK hynix’s iHBM cooling architecture. The concept embeds thermally conductive, electrically insulating blocks into the base die’s die-to-die (D2D) PHY region—the interface hotspot where power density peaks—claiming a thermal resistance reduction of more than 30%. Lee benchmarked iHBM directly against Samsung’s Heat Path Block approach, which routes heat through dedicated pillars, and Micron’s base-die circuit redesign, which claims over 20% improved energy efficiency. All three vendor solutions are targeted for HBM5, with neither expected to reach mass production before 2028. However, because the thermal blocks sit inside the package alongside the D2D PHY, they require co-optimization with the customer’s design and cannot be retrofitted to architectures already in development. “It’s a kind of good option that we can do, but this is not something that we can apply [to] the generation that we already [have] in design,” Lee stated.

During the Q&A session, Tanj Bennett of SemiAnalysis questioned whether stacking taller HBM arrays dilutes effective silicon throughput. He noted that while DRAM operating at the cell level delivers roughly 20 TB/s per square centimeter, a 20-Hi stack tops out around 4 TB/s, and HBM consumes significantly more manufacturing capacity than equivalent DDR5 or LPDDR. “As you get to 20 high, the average speed of that memory is slower than DDR5,” Bennett said. “Why is it better to be using the height of the HBM stack instead of intelligently placing cheaper memory around it?” Lee responded that training workloads demand both high bandwidth and large capacity, while inference may split the difference by keeping KV caches in high-bandwidth memory and offloading other data to LPDDR. This tiered approach is already implemented in platforms like Nvidia’s Vera Rubin, which pools LPDDR5X with HBM4 over NVLink-C2C. Additionally, SK hynix co-developed the High Bandwidth Flash specification with Sandisk to extend memory tiering to NAND storage. “That’s a kind of question that we need to also look at in the future,” Lee acknowledged regarding tiered architectures. According to January reporting, SK hynix holds approximately 70% of Nvidia’s HBM orders for the Vera Rubin generation, all of which will utilize MR-MUF stacking. Lee confirmed that the company has not yet decided which product line will transition away from MR-MUF first.