Nvidia Vera Rubin HBM4: Jensen Huang Confirms All Three Suppliers in Production for Q3 Ship

Jensen Huang arrived at Seoul’s Gimpo Business Aviation Center on Friday, delivering the clearest supply-chain signal yet for the AI infrastructure cycle: all three of the world’s leading memory manufacturers are now qualified, actively producing, and competing to supply high-bandwidth memory 4 (HBM4) chips for Nvidia’s Vera Rubin AI server platform. First systems are scheduled to ship in Q3 2026.

“All three vendors have been qualified,” Huang told reporters at the airport upon arriving from Computex 2026 in Taipei. “All three vendors are in production, and they’re all racing to support Vera Rubin.” The statement ended months of supply-chain speculation and marked the first time Huang publicly confirmed that Samsung Electronics, SK hynix, and Micron Technology are all cleared to supply HBM4 for the same platform. The remarks were reported by Reuters and corroborated by Bloomberg.

Vera Rubin entered full production following Huang’s GTC Taipei keynote on June 1, when Nvidia announced customer shipments would begin in Q3 of this year. Huang characterized the second half of 2026 as a major production ramp, noting output would significantly exceed the first half, with 2027 expected to be even larger. This trajectory requires tight coordination across both DRAM and HBM supply chains.

### How HBM4 Memory Works: Architecture Behind Vera Rubin

HBM4 marks the sixth generation of high-bandwidth memory and represents a structural departure from its predecessor rather than an incremental speed increase.

Under the JEDEC JESD270-4 standard, HBM4 doubles the memory interface width from 1,024 bits—the configuration used in HBM3E chips powering current Grace Blackwell servers—to 2,048 bits, while expanding independent data channels from 16 to 32. This wider bus enables HBM4 to deliver at least 2 terabytes per second of bandwidth per memory stack under the JEDEC baseline specification. Samsung’s production HBM4, built on a 4-nanometer logic die with 12-high DRAM stacking, operates at 11.7 gigabits per second per pin and achieves 3.3 terabytes per second, substantially exceeding the specification floor.

The architecture separates command and data buses to reduce latency during the simultaneous multi-channel memory operations that define large-scale AI training and inference workloads. Each Vera Rubin NVL72 rack contains 20.7 terabytes of HBM4 memory, delivering 1.6 petabytes per second of aggregate bandwidth—a more than 2.7-fold improvement over the 8 terabytes per second provided by HBM3E in Grace Blackwell systems.

The manufacturing process that enables these specifications at scale also presents their greatest constraint. HBM4 stacks DRAM dies vertically using through-silicon vias—microscopic copper pillars that transfer data between layers without the signal-integrity losses typical of conventional board traces. The 12-high stacks currently shipped by Samsung and SK hynix require each silicon die to be thinned to approximately 50 micrometers. Both companies are now racing to qualify 16-high stacks for Vera Rubin Ultra, the follow-on platform slated for late 2027. Those advanced stacks require thinning to roughly 30 micrometers—about half the diameter of a human hair—while maintaining a total package height under the JEDEC-mandated limit of approximately 720 micrometers to fit within standard CoWoS silicon interposer packaging.

### How Vera Rubin Compares to Grace Blackwell

Vera Rubin is not merely a faster iteration of Nvidia’s current Grace Blackwell platform; it is a distinct class of system engineered specifically for what Nvidia terms “agentic AI” workloads—tasks in which a single user prompt triggers hundreds or thousands of autonomous reasoning, retrieval, and tool-use steps before a final response is generated.

Each NVL72 rack integrates 72 Rubin GPUs and 36 Vera CPUs within a liquid-cooled, rack-scale architecture. Every Rubin GPU features 336 billion transistors, delivers 50 petaflops of NVFP4 inference performance, and connects via NVLink 6, which supplies 3.6 terabytes per second of all-to-all scale-up bandwidth per GPU—more than double the NVLink 5 bandwidth found in Blackwell. Nvidia’s stated performance targets include 10 times higher inference throughput per watt compared to Grace Blackwell, 10 times lower cost per inference token, and a requirement for only one-quarter the number of GPUs to train large mixture-of-experts models. For hyperscalers operating inference at scale, where annual electricity costs for a single rack can exceed $2 million, these efficiency gains directly shape capital planning. Huang confirmed that Grace Blackwell systems are deploying successfully alongside the Vera Rubin ramp, positioning the two generations as overlapping supply windows rather than sequential replacements.

### SK Hynix, Samsung, and Micron: A Three-Way Production Race

Industry analysts estimate that SK hynix commands roughly 60 to 70 percent of the HBM4 volume allocated to Vera Rubin, Samsung holds approximately 25 to 30 percent, and Micron supplies the remainder—though Nvidia has not released official allocation figures. These projections reflect a competitive landscape shaped by years of qualification history: SK hynix has served as Nvidia’s primary HBM supplier across prior generations, capturing approximately 62 percent of the overall HBM market as of mid-2025.

Samsung’s position is more complex. The company was the first to initiate HBM4 mass production, announcing commercial shipments on February 12, 2026. Leveraging its 4-nanometer logic die and 12-high stacking process, Samsung achieved 3.3 terabytes per second—the fastest HBM4 specification publicly announced to date. Samsung is also the first to ship HBM4E samples, an enhanced next-generation standard targeting 3.6 terabytes per second at 16 gigabits per second, positioning it for the Vera Rubin Ultra platform in 2027.

SK hynix employs a different bonding methodology for HBM production: Mass Reflow Molded Underfill, a process that has proven more scalable than Samsung’s hybrid bonding approach. Hybrid bonding eliminates traditional solder microbumps between layers to reduce electrical resistance and improve signal density. While hybrid bonding offers structural advantages for denser stacks, it has encountered early yield challenges—demonstrating why Samsung’s technological lead does not automatically convert into a larger production allocation.

Micron, the smallest of the three by HBM market share, has emerged as a critical third supplier. The company has committed to selling out its entire HBM production capacity for 2026 and previously projected an HBM annualized revenue run-rate approaching $8 billion.

### Nvidia Seoul R&D Center, Robotics, and RTX Spark

Huang’s Seoul visit extended beyond HBM supply-chain coordination. He announced that Nvidia has begun recruiting for a research and development center in Seoul, with plans to construct a physical facility once staffing reaches sufficient scale. Describing South Korea’s manufacturing prowess as the foundation for a major physical AI partnership agenda, Huang noted the center will focus on physical AI and robotics research. Nvidia’s Jetson Thor robotics processor—currently deployed by Hyundai Motor Group and LG—will serve as a key platform for industrial applications in the region. Huang told reporters that robotics represents Korea’s next major growth sector, citing the nation’s unique combination of advanced manufacturing and AI capabilities as ideally suited for the physical AI era.

That evening, Huang dined with the chairs of SK Group, LG Group, and Naver at a casual pork-belly barbecue restaurant in Seoul. It marked the second informal gathering in seven months, following his widely noted fried-chicken-and-beer meeting in Korea last October.

Earlier in the day, Huang visited T1 Base Camp, an esports gaming café in Seoul’s Mapo district, to meet Lee “Faker” Sang-hyeok—the six-time League of Legends World Champion—and present him with a personally signed GeForce RTX 5090 graphics card. The visit also served as a platform introduction for RTX Spark, Nvidia’s new AI notebook superchip unveiled at Computex.

RTX Spark is a 70-billion-transistor system-on-chip fabricated on TSMC’s 3-nanometer process. It fuses a 20-core Grace Arm CPU with a Blackwell GPU featuring 6,144 CUDA cores and fifth-generation Tensor Cores capable of 1 petaflop of FP4 AI performance. The CPU and GPU communicate over NVLink-C2C at 600 gigabytes per second—approximately five times the bandwidth of PCIe Gen 5—supported by 128 gigabytes of unified LPDDR5X memory operating at 300 gigabytes per second. This unified memory architecture eliminates the data-transfer bottleneck inherent in discrete GPU-CPU communication over separate buses, enabling the platform to execute large AI workloads and on-device agents without cloud dependency. Huang described RTX Spark as the first fundamental redesign of the personal computer in four decades: a laptop platform engineered from the ground up for an on-device AI agent that functions as a proactive personal assistant rather than a passive tool.