Google and Amazon backing Intel EMIB packaging for inference workloads while Nvidia maintains training on TSMC CoWoS.

A split has been quietly forming in the AI chip supply chain over the past two years: Nvidia's flagship training processors continue to rely on TSMC's CoWoS, while Google, Amazon, Cisco, SpaceX, and Tesla have committed to Intel's Embedded Multi-die Interconnect Bridge (EMIB) for their inference-class chips and custom AI processors. This divergence reflects not capacity constraints but a workload verdict rooted in underlying engineering geometry.

Until recently, TSMC's CoWoS was the only viable packaging option at scale, and securing a CoWoS allocation represented the competitive barrier. Lead times for non-Nvidia customers still stretch 52 to 78 weeks, with TSMC's capacity sold out through 2026 and well into 2027. Rather than queue indefinitely, hyperscaler ASIC teams have examined what their chips actually require—and found that Intel's approach meets those needs more naturally, at lower cost, and at package sizes that CoWoS cannot efficiently serve.

Training accelerators like Nvidia's Blackwell and Rubin run matrix multiply operations continuously at enormous scale, cycling data between compute units and high-bandwidth memory at terabyte-per-second rates. CoWoS's full silicon interposer—with thousands of copper-filled through-silicon vias providing the densest electrical connections between logic die and stacked memory—is purpose-built for this workload.

Inference accelerators and hyperscaler custom chips have different requirements. They need more memory stacks and compute dies in a single package to handle parallel production inference workloads running many simultaneous requests. At larger package sizes and higher volumes—Google's 2028 TPU order from Intel reportedly exceeds three million units—CoWoS's cost and geometry become problematic.

EMIB embeds small silicon bridges directly into the organic package substrate only where adjacent dies need high-speed data exchange. Unlike CoWoS, there is no silicon layer spanning the entire package floor and no separate redistribution layer interposer that must be built, diced, and bonded separately. This elimination removes assembly complexity (CoWoS requires two bonding steps; EMIB requires one), reduces the primary cost driver (the silicon interposer represents 40 to 60 percent of CoWoS package cost), and removes the round-wafer geometry constraint limiting CoWoS package sizes.

CoWoS interposers are manufactured on standard 300mm round wafers. Rectangular AI accelerator packages—now exceeding 5.5 times the photolithography reticle limit, or roughly 4,700 square millimeters—yield only one or two interposers per wafer, achieving roughly 60 percent substrate utilization. Intel's EMIB bridges live inside organic package substrates that come in rectangular panels (approximately 510mm by 515mm), which pack rectangular packages without geometric waste, achieving nearly 90 percent utilization. As packages grow larger with each generation, CoWoS's geometric disadvantage worsens while EMIB's advantage scales proportionally. This structural mechanism explains Intel's 50 percent cost claim and why that advantage does not shrink as chip complexity increases.

TSMC's CoWoS-L variant—powering Blackwell and Rubin—partially addressed this problem with a hybrid design: an organic redistribution layer with small "local silicon interconnect" bridges embedded only where necessary. CoWoS-L scales to 5.5 times the reticle limit (approximately 4,720 square millimeters), with a roadmap to 9.5 times reticle limit (approximately 8,150 square millimeters) in 2027. However, the redistribution layer remains built on a round 300mm wafer, perpetuating the geometry problem.

Intel's EMIB-T already supports packages exceeding 8 times the reticle limit (approximately 6,860 square millimeters)—ahead of TSMC's current ceiling—with a roadmap to packages exceeding 12 times reticle scale by 2028, accommodating 24 or more HBM stacks and 38 or more EMIB-T bridge connections. EMIB-T adds through-silicon vias through the embedded bridges for vertical power delivery, enabling multi-kilowatt package power budgets required by next-generation AI chips.

For years after TSMC's capacity crunch began in 2023, EMIB remained credible in principle but unproven at the volume and yield required by hyperscalers. In mid-July 2026, supply-chain checks by KeyBanc Capital Markets indicated that EMIB-T yield had reached approximately 98 percent—up from roughly 90 percent weeks earlier, surpassing the mass-production yield standard required for commercial viability at hyperscale volume. Packaged AI chips combine high-value logic dies with multiple high-bandwidth memory stacks; a failed package means losing all components inside it. Yield above 98 percent bounds that loss and makes it manageable.