중국의 Kaifa Technology가 월 1만 웨이퍼를 목표로 하는 2.5D 칩릿 첨단 패키징 확대에 18.5억 위안을 투자한다.

Kaifa Technology (000021.SZ) announced a major expansion into advanced packaging on September 9, signaling renewed momentum in a critical semiconductor segment. The company's wholly-owned subsidiary, Payton Technology (Shenzhen) Co., Ltd., plans to invest 1.85 billion yuan (approximately $276.2 million) to expand high-end memory chip packaging and testing capacity, including 10,000 wafers per month of new 2.5D advanced packaging capability. The announcement places Kaifa alongside peers Tongfu Microelectronics (002156.SZ) and Huatian Technology (002185.SZ) in a wave of similar capacity expansions.

The investment splits into two phases: 1.22 billion yuan ($182.2 million) will establish a new wholly-owned subsidiary and manufacturing facility capable of handling 90,000 wafers per month of traditional packaging and testing, plus the 10,000 wafers monthly of 2.5D advanced packaging. An additional 630 million yuan ($94.1 million) will fund a dedicated 2.5D/3DS R&D production line, expected to deliver 100 wafers per month each of 2.5D and 3DS capacity at full scale.

Kaifa's core businesses span memory semiconductors, high-end manufacturing, and smart metering terminals, with its memory segment focused on packaging and testing of DRAM, NAND Flash, and embedded memory chips. The emphasis on 2.5D, 3DS, and "advanced packaging" in the announcement quickly fueled speculation about HBM (High Bandwidth Memory) involvement. Yet Kaifa has tempered expectations: in a June 30 statement on abnormal stock volatility, the company characterized HBM technology as remaining in the R&D phase with no near-term revenue or profit expectations. The announcement provided no clarity on whether planned 2.5D/3DS capacity targets HBM or other applications, nor the timeline for transitioning development into production. As of September 11, Kaifa's shares closed at 35.03 yuan, down 4.03%, valuing the company at 55.516 billion yuan ($8.3 billion).

**Why Advanced Packaging Matters**

2.5D and 3D packaging represent fundamentally different approaches to three-dimensional chip integration. 2.5D typically uses an interposer to connect different chips or components horizontally; 3D stacks multiple chips vertically. Rising demand for high bandwidth and rapid interconnect in AI accelerators has made HBM a central driver of advanced packaging adoption. HBM typically integrates with compute chips such as GPUs and AI accelerators via 2.5D interposers to achieve significantly higher memory bandwidth.

Historically, semiconductor performance gains came primarily from shrinking process nodes. Today, advancing Moore's Law has become prohibitively expensive, forcing the industry toward an alternative: instead of relentless transistor miniaturization, connecting more chips at higher density. Research from Guotai Haitong notes that as chip counts, interconnect density, and system complexity grow, advanced packaging is shifting from a manufacturing support function into the core platform enabling heterogeneous integration.

The addressable market is substantial. The World Semiconductor Trade Statistics forecasts the global semiconductor market will reach $1.51 trillion in 2026, with memory exceeding $800 billion. Fortune Business Insights projects the global advanced packaging market at $45.13 billion in 2025, growing from $48.75 billion in 2026 to $94.33 billion by 2034—a compound annual growth rate of 8.6%.

**A Crowded Capacity Race**

The industry trend has triggered a capacity arms race among Chinese OSAT vendors. This year alone, Tongfu Microelectronics committed 888 million yuan ($132.6 million) to memory chip packaging and testing; Huatian Technology's controlling subsidiary announced 3 billion yuan ($448.0 million) for a memory IC packaging and testing facility; and now Kaifa adds 1.85 billion yuan. The scale of simultaneous investment raises questions about supply-demand balance.

Zhang Xiaorong, president of the Deep Tech Research Institute, highlighted the technical significance of Kaifa's 630 million yuan 2.5D/3DS R&D line, noting that 2.5D/3D packaging involves demanding processes—TSV, micro-bump bonding, and RDL among them—where few Chinese companies possess proven capabilities. He noted that Shenzhen Payton has demonstrated 8-layer and 16-layer stacking, validated HBM samples from certain customers, and already performs packaging and testing for Chinese-manufactured memory products. This suggests Kaifa possesses foundational capabilities to enter the HBM supply chain, though as a packaging and testing provider rather than an HBM manufacturer. "The technical bar is not low, but there remains distance from HBM mass production," Zhang observed.

By 2028, Kaifa's planned 10,000 wafers per month of 2.5D capacity would rank it in the latter portion of China's first tier, comparable to Tongfu's current trajectory. Globally, Zhang estimates TSMC's CoWoS capacity could reach 120,000 to 140,000 wafers per month by end-2026, with total global capacity approaching 200,000 wafers monthly. By that measure, Kaifa's new capacity represents roughly 5% of global related capacity.

Concerns about concentrated deployment are mounting. Wu Zihao, a senior semiconductor industry analyst, noted that multiple Chinese firms—including SJ Semiconductor, JCET (600584.SS), Tongfu, Forehope Electronic (688362.SS), and Kaifa—are simultaneously building 2.5D lines. SJ Semiconductor has achieved relatively early industrialization of 2.5D packaging domestically and already captures a significant share of domestic demand. If these projects come online together, China risks developing 2.5D capacity well beyond actual demand.

**The Foundry Consolidation**

Beyond capacity, the more consequential shift lies in control of the advanced packaging supply chain, according to Wu. Foundries are likely to increasingly dominate advanced packaging—not merely because of the technology itself, but because 3D stacking penetrates deeper into chip design and manufacturing. Parameters like TSV placement, power delivery networks, thermal distribution, and inter-die timing coordination require co-planning at the design phase and consideration at the RTL (register-transfer level) stage. For IDMs and foundries possessing both wafer manufacturing and advanced packaging capabilities, this synergy spanning design, wafer fabrication, and assembly is difficult for traditional OSAT vendors to replicate through capacity expansion alone.

This dynamic already defines the global landscape. TSMC's CoWoS-led advanced packaging business commands substantial market share; Intel deploys EMIB and Foveros technologies; Samsung develops I-Cube and X-Cube approaches. ASE, SPIL, and Amkor remain confined to lower-margin segments—substrate-level assembly and wafer bumping—that TSMC declines to handle. The competitive battle may no longer be a capacity race among OSAT vendors, but rather a consolidation of advanced packaging control by integrated manufacturers.