Huawei disclosed a fresh path to advance semiconductor design, circumventing US export controls on cutting-edge AI accelerators.
As global chip companies approach physical limits in miniaturization, Huawei Technologies is pursuing an alternative path: improving transmission speeds between system components rather than continuing to shrink transistors. Industry experts view this approach as a systematic, replicable innovation strategy taking shape across China's semiconductor, memory, AI, and system integration sectors.
Liao Heng, Huawei's chief semiconductor scientist, noted in a recent interview that decades of transistor shrinkage have nearly reached physical extremes, with transistors now approaching atomic scales. While Western companies rely on ASML's advanced lithography equipment enabled by multiyear roadmaps, Huawei has pursued a more creative approach due to US export sanctions preventing access to such machinery.
Huawei's solution is its "Tau Scaling Law," proposed in May, which shifts focus from chip dimension reduction to improving transmission speeds between system components. The company plans to unveil its first smartphone chip designed under this framework in September, utilizing LogicFolding technology. Liao said industry research companies will dissect this chip later this year, providing clarity on how Huawei's alternative approach closes the gap with competitors.
Liao proposed an "18-story pagoda" framework to illustrate the AI value chain, positioning it as more comprehensive than Nvidia CEO Jensen Huang's five-layer cake model. Huang's model divides the AI industry into five layers—energy, chips, computing infrastructure, cloud/AI models, and applications—as a top-down business framework illustrating value flow culminating in application-layer returns.
Liao's 18-story pagoda operates as a bottom-up engineering framework spanning the entire semiconductor value chain: from foundational elements like theory, energy, and raw materials through silicon and transistor design; wafer fabrication, lithography, and equipment; advanced packaging; chip architecture and runtime environments; quantization; and finally AI training methods, foundation models, agents, products, and commercial applications.
Critically, Liao emphasized that industry performance ceilings are determined by the weakest link in this chain, which varies by geography. Zhou Jianjun, professor at Shanghai Jiao Tong University's School of Integrated Circuits, noted the strategic implications: Huawei seeks performance improvement through system-level optimization rather than further transistor miniaturization.
Xiang Ligang, director-general of the Information Consumption Alliance, contrasted the frameworks: Huang's model frames AI as market opportunity to be captured layer by layer, while Liao's pagoda frames it as an integrated engineering challenge where no single layer can be optimized in isolation. For Huawei, this holistic view proves practical, with breakthroughs in cross-layer collaboration—leveraging system cluster advantages to compensate for individual chip hardware shortcomings.
According to International Data Corp's latest report, China's AI accelerator market shifted dramatically in 2025 due to US export controls. Domestic Chinese suppliers, led by Huawei, captured 41 percent combined market share, while Nvidia's share fell to 55 percent from its near-monopoly levels.