IBM announces breakthrough sub-1nm (0.7nm/7Å) chip technology with revolutionary 3D vertical transistor stacking (NanoStack), achieving 100 billion transistors on a fingernail-sized die—2x density vs. 2021's 2nm process.

IBM has announced a breakthrough sub-1nm chip technology, achieving the industry's first sub-1-nanometer process node at 0.7nm (7 Angstroms). The technology employs a revolutionary 3D vertical transistor stacking architecture called NanoStack to achieve unprecedented density.

The new process enables approximately 100 billion transistors to be integrated on a fingernail-sized die. This represents a 2x increase in transistor density compared to IBM's 2nm process announced in 2021, marking a significant leap in semiconductor miniaturization.

For AI infrastructure, this breakthrough enables higher computational density in processor designs—a critical requirement as AI workloads demand increasingly powerful chips. Greater transistor density translates to more computational capability in smaller, more efficient form factors, directly addressing the cost and power constraints driving AI compute infrastructure expansion.